LMH1983 Datasheet, PDF (44/55 Pages) National Semiconductor (TI) – Generating 44.1 kHz Based highly integrated programmable audio

LMH1983
SNLS309I – APRIL 2010 – REVISED DECEMBER 2014
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11.2 Layout Example
Vdd3_3
R1
0
Do Not Load
C5
1 µF
C8
Vdd3_3
VddPLL1
VddCLK1
VddCLK2
VddPLL2
VddCLK3
VddPLL3
VddCLK4
C1
C2 ^{1 µF}
0.1 µF
C3
C4 ^{1 µF}
0.1 µF
C6
C7 ^{1 µF}
0.1 µF
GND
R2
0
Do Not Load
Hsync
Vsync
Fsync
GND ^INIT
SDA
SCL
3 _Vin
4 _Hin
5
6
Fin
INIT
7
8
9
ADDR
SDA
SCL
Vdd3_3
R4
3.0k
R7
1.8k
34
33
XOin+
XOin-
0.1 µF
U1
LMH1983SQ
Fout1
CLKout1+
CLKout1-
37
36
35
Fout2
CLKout2-
CLKout2+
30
29
28
CLKout3-
CLKout3+
Fout3
24
23
22
Fout4/OSCin
CLKout4+
CLKout4-
17
15
14
NO_REF
NO_ALIGN
NO_LOCK
13
12
11
VC_LPF ⁴⁰
VddVCXO
GND
Fout1
CLK1_P
CLK1_N
Fout2
CLK2_P
CLK2_N
CLK3_N
CLK3_P
Fout3 _{Vdd3_3}
Fout4
CLK4_P
CLK4_N
NOREF
NOALIGN
NOLOCK
R5
10.0k
5
3
CP
CS
47 µF
4
1 µF
RS
17.4k
GND
U2
LMP7711MK
V-
1
V+
Vdd3_3
GND
GND
5 _OUTA
R10
4 _OUT
49.9
VC ¹
GND
X1
GND
357LB3I027M0000
C12
0.1 µF
GND
Figure 33. LMH1983 Typical Interface Circuit
An example of a typical application circuit for the LMH1983 is shown in the Figure 33. When performing PCB
layout, key areas to consider regarding this circuit are the loop filter – which consists of R_S, C_S, C_P and the
LM7711 Operational Amplifier which buffers the loop filter output prior to driving the control voltage input of the
VCXO. Care must be taken in the component selection for the loop filter components (see VCXO Selection
Criteria and Loop Filter Capacitors). The CLKout outputs are differential LVDS signals and should be treated as
differential signals. These signals may be laid out as fully differential lines, in which the characteristic impedance
between the two lines is nominally 100 Ω. Alternately, loosely coupled lines may be used, in which case the
characteristic impedance of each line should be 50 Ω referenced to GND. In either case, care should be taken to
match the lengths of the traces as closely as possible. Trace length mismatches on a differential line will add to
the jitter seen on that line. Jitter is also added to the clock outputs if other signals are allowed to interfere with the
signal traces. Therefore, to the greatest extent possible, the clock traces should be isolated from other signals.
Long parallel runs should also be avoided. In places where a hostile signal must cross a sensitive clock signal, it
should be routed such that it crosses as closely as possible to a 90° crossing.
When performing board layouts with the LMH1983, stencil parameters such as aperture area ratio and the
fabrication process have a significant impact on paste deposition. Inspection of the stencil prior to placement of
the WQFN package is highly recommended to improve board assembly yields. If the via and aperture openings
are not carefully monitored, the solder may flow unevenly through the DAP. Stencil parameters for aperture
opening and via locations are shown in Figure 34.
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