LMH1983 Datasheet, PDF (30/55 Pages) National Semiconductor (TI) – Generating 44.1 kHz Based highly integrated programmable audio

LMH1983
SNLS309I – APRIL 2010 – REVISED DECEMBER 2014
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Register Map (continued)
ADD NAME
0x1B
Loss of Reference
Threshold
0x1C Loss of Lock Threshold
0x1D
Mask Control – PLL Lock
and Output Align
0x1E Reserved
0x1F Reserved
0x20 Input Format
0x21
Output Frame Lookup –
Input Vsync Code
0x22
Output Frame Lookup –
PLL2 Vsync Code
0x23
Output Frame Lookup –
PLL3 Vsync Code
0x24 Reserved
Table 3. LMH1983 Register Map (continued)
BITS
7
6:4
3
FIELD
RSVD
HSYNC_Missing
Threshold
RSVD
2:0 LOR_Threshold
7:5 RSVD
4:0 LOCK1_Threshold
7
MASK_LOCK4
6
MASK_LOCK3
5
MASK_LOCK2
4
MASK_LOCK1
3
MASK_TOF4_ALIGN
2
MASK_TOF3_ALIGN
1
MASK_TOF2_ALIGN
0
MASK_TOF1_ALIGN
7:0 RSVD
7:0 RSVD
7:6 RSVD
5:0 Input Format
7:4 RSVD
3:0 Input Vsync Code
7:4 RSVD
3:0 PLL2 Vsync Code
7:4 RSVD
3:0 PLL3 Vsync Code
7:0 RSVD
R/W DEFAULT
DESCRIPTION
0
Reserved
R/W
00
Sets the threshold for number of additional clocks to wait
before setting HSYNC_Missing.
0
Reserved
Sets the number of Hsync periods to wait before setting loss
R/W
001
of reference. Since during blanking there can have up to 5
missing Hsync pulses, this value is usually set to 6.
000
Reserved
Sets the number of Hsync periods to wait before setting loss
R/W
10000 of lock. Since during blanking there can have up to 5 missing
Hsync pulses, this value is usually set > 6.
R/W
0
Setting this bit masks the PLL4 lock status in the global
LOCK_STATUS bit.
R/W
0
Setting this bit masks the PLL3 lock status in the global
LOCK_STATUS bit.
R/W
0
Setting this bit masks the PLL2 lock status in the global
LOCK_STATUS bit.
R/W
0
Setting this bit masks the PLL1 lock status in the global
LOCK_STATUS bit.
R/W
0
Setting this bit masks the TOF4 align status in the global
ALIGN_STATUS bit.
R/W
0
Setting this bit masks the TOF3 align status in the global
ALIGN_STATUS bit.
R/W
0
Setting this bit masks the TOF2 align status in the global
ALIGN_STATUS bit.
R/W
0
Setting this bit masks the TOF1 align status in the global
ALIGN_STATUS bit.
0x00
Reserved
0x00
Reserved
00
Reserved
000000
When Auto Format Detection is enabled (EN_AFD, address
0x05), this register is read-only and controlled automatically.
When Auto Format Detection is disabled, this register is
writable via I²C.
All writes to this register (whether automatic or manual) will
update all the LUT1 (Lookup Table 1), LUT2_2, and LUT2_3
output registers based on the value written here. Writing to
any of the LUT1, LUT2_2, or LUT2_3 output registers will set
this field to 6’d62 (0x3E) indicating that custom changes have
been made.
00
Reserved
Writes to this register update the Vsync code which tells the
device what the Input frame rate is. There is a table which
R/W
0011
correlates the Vsync codes to the actual frame rates. When
Auto Format Detection is enabled (EN_AFD, address 5), this
register is read-only, and is automatically loaded by the
device.
00
Reserved
Whenever PLL2_FORMAT (address 7) is written, this field is
R/W
0101
updated with the appropriate Vsync code. If any custom
changes are made the device will set this field to 4’d14 (0x0E)
to so indicate.
0000 Reserved
Whenever PLL3_FORMAT (address 8) is written, this field is
R/W
0110
updated with the appropriate Vsync code. If any custom
changes are made the device will set this field to 4’d14 (Ox0E)
to so indicate.
0x00
Reserved
30
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