LMH1983 Datasheet, PDF (16/55 Pages) National Semiconductor (TI) – Generating 44.1 kHz Based highly integrated programmable audio

LMH1983
SNLS309I – APRIL 2010 – REVISED DECEMBER 2014
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Feature Description (continued)
8.3.5 Clock Output Jitter
Many circuits that require video clocks, such as the embedded Serializers and Deserializers found in FPGAs, are
sensitive to jitter. In all real world applications, jitter has a random component, so it is best specified in statistical
terms. The SMPTE serial standards (SMPTE 259M, SMPTE 292M and SMPTE 424M) use a frequency domain
method of specifying jitter where they refer to the peak-to-peak jitter of a signal after the jitter has been bandpass
filtered. Jitter at frequencies below 10 Hz is ignored, and the jitter in a band from 10 Hz to an intermediate
frequency (1 kHz for the 270 Mbps standard, 100 kHz for the 1.5 Gbps and 3 Gbps standards) is referred to as
timing jitter. Jitter from the intermediate frequency up to 1/10 of the serial rate is referred to as alignment jitter.
The limits that the SMPTE standards place are peak-to-peak limits, but especially at the higher rates, random
processes have a significant impact, and it is not possible to consider peak-to-peak jitter without a corresponding
confidence level. The methodology used to specify the jitter on the LMH1983 decomposes the jitter into a
deterministic component (t_DJ) plus a random component (t_RJ). This is the methodology used by the jitter analysis
tools supported on high bandwidth oscilloscopes and timing analysis tools from major instrumentation
manufacturers.
To convert between RMS jitter and peak-to-peak jitter, the Bit Error Rate (BER) must be specified. Since jitter is
a random event, without a known BER, the peak-to-peak jitter will be dependent upon the observation time and
can be arbitrarily large. The equation that links peak-to-peak jitter to RMS jitter is:
t_P-P= t_DJ+α*t_RJ
(8)
where α is determined by the BER according to the equation:
1/2erfc(√2*α) = BER
(9)
The erfc (error function) can be found in several mathematics references and is also a function in both Excel and
MATLAB. A fairly common BER used for these calculations is 10^-12, which yields a value of α = 14.
Another common method for evaluating the jitter of a clock output is to look at the phase noise as a function of
frequency. Plots showing the phase noise for each of the four CLKout outputs can be found in Figure 1 through
Figure 8.
8.3.6 Lock Determination
There are four bits in Register 0x02 that indicate the lock status of the four PLLs. Lock determination for PLL1
can be controlled through two registers: LockStepSize (Register 0x2D) and Loss of Lock Threshold (Register
0x1C). The LockStepSize register sets the amount of variation that is permitted on the VC_LPF pin while still
considering the device to be locked. If the reference to the LMH1983 has a large amount of jitter, then the device
may be unable to declare lock because the LockStepSize is set too low. The second register, the Loss of Lock
Threshold register, controls the lock state declaration of PLL1. This register sets a number of cycles on the H_IN
input that must be seen before loss of lock is declared. For some reference signals, there can be several missing
H_IN pulses during vertical refresh. Therefore, it is suggested that this register be loaded with a value greater than
six (Loss of Lock Threshold > 6). Pin 11, NO_LOCK, gives the lock status of the LMH1983. Note that the status
of the NO_LOCK pin can also be read from Register 0x01, and it is a logical OR of the four individual NO_LOCK
status bits of the four PLLs. The NO_LOCK status pin is masked by the bits in the PLL Lock mask (Register
0x1D), and the status is also masked if an individual PLL is powered down.
8.3.7 Lock Time Considerations
The lock time of the LMH1983 is dominated by the lock time of PLL1. The other PLLs have much higher loop
bandwidths, and as a result, they lock more quickly than PLL1 does. Therefore, lock time considerations mainly
rely on PLL1. The lock time for a PLL is dependent upon the loop bandwidth (see Equation 1). A small loop
bandwidth typically increases the time required to achieve lock. To counter this issue, the LMH1983 also allows a
Fastlock mode. In this mode, the bandwidth is increased by increasing the charge pump current when the loop is
unlocked. Then, at a time programmed by the user after lock is declared, I_CP1 is throttled back to drop the
bandwidth to the desired set point. The result is both fast lock time and very low residual jitter.
Another factor when considering lock time is whether 'drift lock' has been enabled or not (see TOF1 Alignment).
If drift lock is enabled and there is a significant difference in the phase of TOF1 relative to the F_IN signal, the
VCXO is slewed to ramp the clock rate up or down until the two framing signals are brought into alignment. It is
possible that this process may take a long time (tens of seconds).
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