LMH1983 Datasheet, PDF (32/55 Pages) National Semiconductor (TI) – Generating 44.1 kHz Based highly integrated programmable audio

LMH1983
SNLS309I – APRIL 2010 – REVISED DECEMBER 2014
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Register Map (continued)
ADD
0x33
NAME
PLL3 Advanced Control
VCO Range
0x34
PLL4 Advanced Control
Main
0x35
PLL4 Advanced Control
Charge Pump Current
0x36
PLL4 Advanced Control
R counter
0x37
PLL4 Advanced Control
N counter MSB
0x38
0x39
PLL4 Advanced Control
N counter LSB
PLL4 Advanced Control
VCO Range
0x3A LVDS Control
0x3B
TOF1 Adv Control
LPF MSB
0x3C
TOF1 Advanced Control
LPF_LSB
0x3D
TOF2 Advanced Control
CPL MSB
0x3E
TOF2 Advanced Control
CPL LSB
0x3F
TOF2 Advanced Control
LPF MSB
0x40
TOF2 Advanced Control
LPF_LSB
0x41
TOF2 Advanced Control
Frame Reset MSB
0x42
TOF2 Advanced Control
Frame Reset LSB
0x43
TOF3 Advanced Control
CPL_MSB
0x44
TOF3 Advanced Control
CPL_LSB
0x45
TOF3 Advanced Control
LPF_MSB
0x46
TOF3 Advanced Control
LPF_LSB
Table 3. LMH1983 Register Map (continued)
BITS FIELD
R/W DEFAULT
DESCRIPTION
7:0 VCO_RNG3
R/W
0x05
Controls the VCO range
7:4 PLL4_DIV
3
PLL4_Disable
2
RSVD
1
IS125M
0
PLL4_Mode
7:4 RSVD
3:0 ICP4
7
RSVD
6:0 DIV_R4
7:2 RSVD
1:0 DIV_N4_MSB
R/W
0010
Controls the PLL4 output divider — PLL4 is divided by
2^PLL4_DIV
R/W
0
0 = PLL4 is enabled
1 = PLL4 is disabled
0
Reserved
R/W
0
0 = 100 MHz clock
1 = 125 MHz clock
R/W
0
0 = using 27 MHz Clock
1 = using external clock
0000 Reserved
R/W
1000 Controls PLL4 Charge Pump Current
0
Reserved
R/W 1001011 Sets the R divider in PLL4
000000 Reserved
R/W
10
Two MSBs of the N divider in PLL4
7:0 DIV_N4_LSB
R/W
0x00
8 LSBs of the N divider in PLL4
7:0 VCO4 Range
7
LVDS Boost
6:4 LVDS_DIFF
3:0 LVDS_CM
7:5 RSVD
4:0 TOF1_LPF_MSB
7:0 TOF1_LPF_LSB
7
RSVD
6:0 TOF2_CPL_MSB
7:0 TOF2_CPL_LSB
7:5 RSVD
4:0 TOF2_LPF_MSB
7:0 TOF2_LPF_LSB
7:5 RSVD
4:0 TOF2_RST_MSB
7:0 TOF2_RST_LSB
R/W
0x16
The value in the VCO4 Range register is used to adjust the
center frequency of PLL4.
R/W
0
Applies pre-emphasis to LVDS output
R/W
100
Adjusts LVDS Differential output swing
R/W
1001 Adjusts LVDS Common Mode output voltage
000
Reserved
5 MSBs of the TOF1 lines per Frame count. This is read-only
R
00010 and loaded automatically when Auto Format Detection is
enabled
8 LSBs of the TOF1 lines per Frame count. This is read-only
and loaded automatically when Auto Format Detection is
R
0x0D
enabled
Together with Register 0x3B this is a 13 bit number which
number of lines per frame. TOF1 will be at a frequency of
Hsync divided by this value.
0
Reserved
R
0001010 _{This 15 bit register gives the number of clock cycles per line to}
calculate TOF2. It is loaded automatically based on the format
R
0x50
set with Register 0x07.
000
Reserved
R
00010 This 13 bit register is loaded automatically based on the
format selected via Register 0x07. It sets the number of lines
R
0x65
per frame for the selected format to set the TOF2 rate
correctly.
000
Reserved
R
00010
Automatically loaded based on formats selected.
R
0x58
7
RSVD
6:0 TOF3_CPL_MSB
7:0 TOF2_CPL_LSB
7:5 RSVD
4:0 TOF3_LPF_MSB
7:0 TOF3_LPF_LSB
0
Reserved
R
0001000 _{This 15 bit register gives the number of clock cycles per line to}
calculate TOF3. It is loaded automatically based on the format
R
0x98
set with Register 0x08.
000
Reserved
R
00100 This 13 bit register is loaded automatically based on the
format selected via Register 0x08. It sets the number of lines
R
0x65
per frame for the selected format to set the TOF3 rate
correctly.
32
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