LMH1983 Datasheet, PDF (1/55 Pages) National Semiconductor (TI) – Generating 44.1 kHz Based highly integrated programmable audio

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LMH1983
SNLS309I – APRIL 2010 – REVISED DECEMBER 2014
LMH1983 3G/HD/SD Video Clock Generator with Audio Clock
1 Features
•1 Four PLLs for Simultaneous A/V Clock Generation
– PLL1: 27 or 13.5 MHz
– PLL2: 148.5 or 74.25 MHz
– PLL3: 148.5/1.001 or 74.25/1.001 MHz
– PLL4: 98.304 MHz / 2^X (X = 0 to 15)
• 3 x 2 Video Clock Crosspoint
• Flexible PLL Bandwidth to Optimize Jitter
Performance and Lock Time
• Soft Resynchronization to New Reference
• Digital Holdover or Free-run on Loss of Reference
• Status Flags for Loss of Reference and Loss of
PLL Lock
• 3.3 V Single Supply Operation
• I²C Interface with Address Select Pin (3 States)
2 Applications
• Triple Rate (3G/HD/SD) SDI SerDes
• FPGA Reference Clock Generation/Cleaning
• Audio Embed or De-embed
• Video Cameras
• Frame Synchronizers (Genlock, DARS)
• A-D or D-A Conversion, Editing, Processing Cards
• Keyers and Logo Inserters
• Format or Standards Converters
• Video Displays and Projectors
• A/V Test and Measurement Equipment
3 Description
The LMH1983 is a highly-integrated programmable
audio/video (A/V) clock generator intended for
broadcast and professional applications. It can
replace multiple PLLs and VCXOs used in
applications supporting SMPTE serial digital video
(SDI) and digital audio AES3/EBU standards. It offers
low-jitter reference clocks for any SDI transmitter to
meet stringent output jitter specifications without
additional clock cleaning circuits.
The LMH1983 features automatic input format
detection, simple programming of multiple A/V output
formats, genlock or digital free-run modes, and
override programmability of various automatic
functions. The recognized input formats include HVF
syncs for the major video standards, 27 MHz, 10
MHz, and 32/44.1/48/96 kHz audio word clocks.
The dual-stage PLL architecture integrates four PLLs
with three on-chip VCOs. The first stage (PLL1) uses
an external low-noise 27 MHz VCXO with narrow
loop bandwidth to provide a clean reference clock for
the next stage. The second stage (PLL2, 3, 4)
consists of three parallel VCO PLLs for simultaneous
generation of the major digital A/V clock fundamental
rates, including 148.5 MHz, 148.5/1.001 MHz, and
98.304 MHz (4 × 24.576 MHz). Each PLL can
generate a clock and a timing pulse to indicate top of
frame (TOF).
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LMH1983
WQFN (40)
6.00 mm × 6.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application Block Diagram
LOOP
FILTER
27 MHz
VCXO
525i
H sync
Analog
ref. in
LMH1981 _{V sync}
Sync
Hin
Vin
Separator F sync Fin
27 MHz (PLL1)
CLKout1 _{29.97 Hz (TOF1)}
148.5 MHz (PLL2)
CLKout2
29.97 Hz (TOF2)
LMH1983
148.35 MHz (PLL3)
CLKout3
59.94 Hz (TOF3)
24.576 MHz (PLL4)
CLKout4
5.994 Hz
FPGA
A/V Frame Sync with
Downconverter,
Audio Embedder and
De-embedder
525i/29.97 SDI out
+ embedded audio
1080p/59.94 SDI out
+ embedded audio
1080p/59.94 SDI in
+ embedded audio
Genlocked to video ref. in
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.