LMH1983 Datasheet, PDF (31/55 Pages) National Semiconductor (TI) – Generating 44.1 kHz Based highly integrated programmable audio

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LMH1983
SNLS309I – APRIL 2010 – REVISED DECEMBER 2014
Register Map (continued)
ADD NAME
0x25 PLL1 Advanced Control
0x26
PLL1 Advanced Control
FastLock Delay
0x27
PLL1 Advanced Control
Fastlock CP Current
0x28
PLL1 Advanced Control
Charge Pump Current
0x29
PLL1 Advanced Control
R Counter MSB
0x2A
PLL1 Advanced Control
R Counter LSB
0x2B
PLL1 Advanced Control
N Counter MSB
0x2C
PLL1 Advanced Control
N Counter LSB
0x2D
PLL1 Advanced Control
Lock Step Size
0x2E
PLL2 Advanced Control
Main
0x2F
PLL2 Advanced Control
Charge Pump Current
0x30
PLL2 Advanced Control
VCO Range
0x31
PLL3 Advanced Control
Main
0x32
PLL3 Advanced Control
Charge Pump Current
Table 3. LMH1983 Register Map (continued)
BITS FIELD
R/W
7:5 RSVD
4
PLL1_DIV
R/W
3
RSVD
2
PLL1 Input Mode
R/W
1
RSVD
0
FastLock
7:4 RSVD
3:0 FastLock Delay
R/W
4:0
FastLock Charge Pump
Current
R/W
4:0
PLL1 Charge Pump
Current
R/W
7:2 RSVD
1:0 MSB
R/W
7:0 LSB
R/W
7
RSVD
6:0 MSB
R/W
7:0 LSB
R/W
7:5 RSVD
4:0 Lock Step Size
R/W
7:5 RSVD
4
PLL2_DIV
R/W
3
PLL2_DISABLE
R/W
2:0 RSVD
7:4 RSVD
3:0 ICP2
R/W
DEFAULT
000
0
0
0
0
1
0000
0000
11111
01000
000000
00
0x01
0
0000110
0xB4
000
01000
000
0
0
000
0000
0010
DESCRIPTION
Reserved
0 = Divide by 1 (Output is 27 MHz)
1 = Divide by 2 (Output is 13.5 MHz)
Reserved
Directly controls the mode of the PLL1 input buffer.
0 = Single Ended
1 = Differential
Reserved
This bit enables ICP1_FAST (address 0x27) to be used during
locking.
0 = FastLock disabled
1 = FastLock enabled
Reserved
Sets the amount of time that PLL1_Lock must be asserted
before the PLL1 Charge pump current is reduced from the
ICP1_Fast value to the ICP1 value. The time delay is specified
in units of half seconds. Delay = FastlockDelay*0.5 Seconds.
Valid values are from 0 to 10. Values from 11 to 15 are
reserved.
This field specifies the charge pump current to drive when
FastLock is active. Charge pump current is equal to 34.375 µA
* register value
This field defines the charge pump current used when
FastLock is not active. Charge pump current is equal to
34.375 µA * register value
Reserved
The two LSBs of Register 0x29 along with the eight bits of
Register 0x2A form a ten bit word which comprises the R
divider for PLL1. This register is internally written based on the
input format and when AutoFormatDetect is enabled, these
registers are read only.
Reserved
The 7 LSBs of Register 0x2B along with the eight bits of
Register 0x2C comprise the fifteen bit word which is used for
the N divider of PLL1. These registers are internally controlled
based on the input format detected and when
AutoFormatDetect is enabled, these registers are read only.
Reserved
See Application Information section discussion on Lock Detect
Reserved
0 = divide by 1
1 = divide by 2
0 = PLL2 disable is determined by XPT_MODE (Address
0x09)
1 = PLL2 is disabled
Reserved
Reserved
Controls PLL2 Charge Pump Current
7:0 VCO_RNG2
R/W
0x0C Controls the VCO range
7:5 RSVD
4
PLL3_DIV
3
ICP3
2:0 RSVD
7:4 RSVD
3:0 ICP3
000
Reserved
R/W
0
0 = divide by 1
1 = divide by 2
0 = PLL3 disable is determined by XPT_MODE (Address
R/W
0
0x09)
1 = PLL3 is disabled
000
Reserved
0000 Reserved
R/W
0011 Controls PLL3 Charge Pump Current
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