LMH1983 Datasheet, PDF (27/55 Pages) National Semiconductor (TI) – Generating 44.1 kHz Based highly integrated programmable audio

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LMH1983
SNLS309I – APRIL 2010 – REVISED DECEMBER 2014
Register Map (continued)
Table 3. LMH1983 Register Map (continued)
ADD NAME
BITS FIELD
7:4 RSVD
3
EN_AUTOPOL
0x06 Input Polarity
2
HIN_POL_OVR
1
VIN_POL_OVR
0
FIN_POL_OVR
0x07
0x08
7:6
Output Mode – PLL2 Format
5:0
7:6
Output Mode – PLL3 Format
5:0
7:5
RSVD
PLL2_Format
RSVD
PLL3_Format
RSVD
0x09 Output Mode – Misc
4
AFS Mode
3:0 XPT_Mode
0x0A Output Buffer Control
7:4 CLK_HIZ
3:0 FOUT_HIZ
0x0B
Output Frame Control –
Offset1_MSB
0x0C
Output Frame Control –
Offset1_LSB
0x0D
Output Frame Control –
Offset2_MSB
0x0E
Output Frame Control –
Offset2_LSB
0x0F
Output Frame Control –
Offset3_MSB
0x10
Output Frame Control –
Offset3_LSB
7:5 RSVD
4:0 TOF1 Offset MSB
7:0 TOF1 Offset LSB
7:5 RSVD
4:0 TOF2 Offset MSB
7:0 TOF2 Offset LSB
7:5 RSVD
4:0 TOF3 Offset MSB
7:0 TOF3 Offset LSB
R/W DEFAULT
DESCRIPTION
0000 Reserved
Enables Auto Polarity Detection and Correction. The proper
polarity needs to be set to synchronize the output timing
signals to the leading edges of the H and V inputs.
R/W
1
0 = The polarities of HVF inputs are manually set by their
respective polarity override registers.
1 = The polarity of the H input is auto-detected. The polarity
correction applied to the H input will also be applied to V and
F inputs.
Used to manually set the H input Polarity.
R/W
0
0 = Active Low (Negative polarity)
1 = Active High (Positive polarity)
Used to manually set the V input Polarity.
R/W
0
0 = Active Low (Negative polarity)
1 = Active High (Positive polarity)
Used to manually set the F input Polarity.
R/W
0
0 = Active Low (Negative polarity)
1 = Active High (Positive polarity)
00
Reserved
R/W
001110 Sets the video format output timing for PLL2.
00
Reserved
R/W
001101 Sets the video format output timing for PLL3.
000
Reserved
Sets the TOF4 output timing mode.
R/W
0
0 = Secondary Audio Clock Output (derived from PLL4 clock)
1 = Audio Frame Sync (derived from TOF1)
R/W
0000
Sets the PLL crosspoint mode for Out2 and Out3.
Refer to Table 4.
[3] sets CLKout4 output buffer mode.
[2] sets CLKout3 output buffer mode.
R/W
0000
[1] sets CLKout2 output buffer mode.
[0] sets CLKout1 output buffer mode.
0 = CLKoutx enabled
1 = CLKoutx Hi-Z
[3] sets Fout4 output buffer mode.
[2] sets Fout3 output buffer mode.
R/W
1111
[1] sets Fout2 output buffer mode.
[0] sets Fout1 output buffer mode.
0 = Foutx enabled
1 = Foutx Hi-Z
000
Reserved
R/W
00000 _{TOF1_Offset[12:0] sets number of lines to delay TOF1.}
TOF1_Offset_MSB[4:0] sets TOF1_Offset[12:8]
R/W
0x00
TOF1_Offset_LSB[7:0] sets TOF1_Offset[7:0]
000
Reserved
R/W
00000 _{TOF2_Offset[12:0] sets number of lines to delay TOF2.}
TOF2_Offset_MSB[4:0] sets TOF2_Offset[12:8]
R/W
0x00
TOF2_Offset_LSB[7:0] sets TOF2_Offset[7:0]
000
Reserved
R/W
00000 _{TOF3_Offset[12:0] sets number of lines to delay TOF3.}
TOF3_Offset_MSB[4:0] sets TOF3_Offset[12:8]
R/W
0x00
TOF3_Offset_LSB[7:0] sets TOF3_Offset[7:0]
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