LMH1983 Datasheet, PDF (42/55 Pages) National Semiconductor (TI) – Generating 44.1 kHz Based highly integrated programmable audio

LMH1983
SNLS309I – APRIL 2010 – REVISED DECEMBER 2014
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REGISTER[Bit(s)]
0x05[5]
0x05[4:3]
0x05[1]
0x07[5:0]
0x08[5:0]
0x11[5:4]
0x11[3:2]
0x12[5:4]
0x13[5:4]
0x34[7:4]
Table 13. SMBus Register Settings for Figure 30
WRITE VALUE
1'b
00'b
1'b
001110'b
001101'b
10'b
01'b
10'b
10'b
0000'b
COMMENTS
Auto Format Detect enabled
PLL1 operating in Free-run mode
Forces PLL2 = 148.5 MHz and PLL3 = 148.35 MHz
Set PLL2 Output to Format Detection Code 14 (0x0E)
Set PLL3 Output to Format Detection Code 13 (0x0D)
Set to always align when misaligned
Drift lock (small misalignment), crash lock (large misalignment)
Set TOF2 to always align when misaligned
Set TOF3 to always align when misaligned
Set PLL4_DIV to divide-by-1 for 98.304 MHz
9.2.3.3 Application Curve
10 ns / div
Traces 1-4: 1 V / div
Figure 31. CLKout 1-4 Signals after Tracking 27 MHz TCXO Reference
42
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