LMH1983 Datasheet, PDF (43/55 Pages) National Semiconductor (TI) – Generating 44.1 kHz Based highly integrated programmable audio

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LMH1983
SNLS309I – APRIL 2010 – REVISED DECEMBER 2014
10 Power Supply Recommendations
It is important to ensure that the LMH1983 is provided with an adequate power supply that provides the cleanest
voltage to the VDD_IO and VDD supply pins. One potential source of jitter on a multiple clock system such as
the LMH1983 is interference among the four PLLs on the chip. To help reduce this effect, each PLL is run from a
separate power supply internally on the LMH1983, and each supply has its own internal regulator. These
regulators each require their own external bypass as seen in Figure 32 with bypass capacitors.
3.3 V
Capacitors can be
either tantalum or an
ultra-low ESR ceramic.
VDD
PLL1
(Pin 1)
VDD_IO
(Pin 2, 10)
3.3 V
3.3 V
3.3 V
3.3 V
VDD
CLKout1
(Pin 38)
VDD
CLKout2
(Pin 31)
VDD
PLL2
(Pin 32)
Internal
LDO
regulator
VDD
CLKout3
(Pin 20)
VDD
CLKout4
(Pin 16)
Cbyp2
(Pin 27)
3.3 V
3.3 V
3.3 V
VDD
PLL3,
PLL4
(Pin 19)
Internal
LDO
regulator
Cbyp3
(Pin 25)
Internal
LDO
regulator
Cbyp4
(Pin 26)
Place 1 µF and 0.1 µF
bypass capacitors as close to
the Cbyp Pin as possible.
Figure 32. LMH1983 Power Supply Connection Diagram
11 Layout
11.1 Layout Guidelines
When designing the PCB layout for the LMH1983, it is important to follow these the guidelines:
• Whenever possible, dedicate an entire layer to each power supply. This will reduce the inductance in the
supply plane.
• Use surface mount components whenever possible.
• Place bypass capacitors and filter components as close as possible to each power pin.
• Place the loop filter components, including the buffer amplifier, and VCXO as close as possible to the
LMH1983.
• Do not allow discontinuities in the ground planes – return currents follow the path of least resistance. For high
frequency signals this will be the path of least inductance.
• Make sure to match the trace lengths of all differential traces.
• Remember that vias have significant inductance — when using a via to connect to a power supply or ground
layer, two in parallel will reduce the inductance over a single via.
• Connect the pad on the bottom of the package to a solid ground connection. This contact is used as a major
ground connection as well as providing a thermal conduit which helps to maintain a constant die temperature.
• See Application Note: AN-1187, Leadless Leadframe Package (LLP) (SNOA401) for more Information on the
LLP (WQFN) style package.
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