LMH1983 Datasheet, PDF (15/55 Pages) National Semiconductor (TI) – Generating 44.1 kHz Based highly integrated programmable audio

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LMH1983
SNLS309I – APRIL 2010 – REVISED DECEMBER 2014
Feature Description (continued)
8.3.3 Control of PLL2 and PLL3
PLL2 and PLL3 have the least amount of flexibility of the four PLLs in the LMH1983. They are pre-programmed
to run at 148.5 MHz and 148.35 MHz respectively. There is a divide-by-two option available to allow the output to
be 74.25 MHz or 74.18 MHz, should these frequencies be required. These two PLLs can also be disabled –
disabling PLL2 or PLL3 can save significant amounts of power if that particular clock is not required. Figure 11
shows a simplified functional block diagram of PLL2 and PLL3.
27 MHz In
÷R
CP
PFD
Current
Source
þ
÷N
VCO
CLK Out
Figure 11. PLL2 / PLL3 Block Diagram
8.3.4 Control of PLL4
Although originally intended to generate only a clock for audio use, PLL4 features much greater versatility.
Several registers may be used to configure PLL4 to generate a broad selection of frequencies. The default state
for PLL4 is to generate 24.576 MHz (48 kHz x 512) on the output of CLK4 and a 5.996 Hz output from TOF4.
This is done by taking CLK1 (27 MHz), and dividing by 75, resulting in a signal of 360 kHz. This frequency is
compared to the internal PLL4 VCO, nominally 1.2 GHz, divided by 4096. The VCO frequency is adjusted via
register control until the resulting frequency yields 360 kHz. The final VCO frequency is then divided by 12 to
generate a 98.304 MHz signal (48 kHz x 2048). Any power of two multiple of 48 kHz can be generated by
changing the contents of the PLL4_DIV component of Register 0x34. Note that the divider here is in powers of 2,
so the default value of 2 results in the 98.304 MHz signal being divided by 2² or 4. The final CLKout4 frequency
is therefore 24.576 MHz. PLL4_DIV is a 4-bit value, so values up to 15 may be programmed, resulting in a divide
by 2¹⁵ or 32,768. If audio clocks based on a 44.1 kHz sampling clock are desired, refer to Application Note
AN–2108, Generating 44.1 kHz Based Clocks with the LMH1983, (SNLA129) for detailed instructions.
TOF4 has two different operation modes. When the AFS_mode bit (Register 0x09) is set to a 0, then TOF4 is
derived by dividing CLKout4 by a value of 2^TOF4_ACLK (Register 0x4A). if the AFS_mode bit is set to 1, then TOF4
is derived from TOF1 — divided by AFS_div (Register 0x49). When AutoFormatDetect is true, then the AFS_div
register is read only and is internally set depending upon the format detected.
27MHz In
÷R
Phase/
Frequency
Detector
Current
Source
Loop Filter
÷(N x 8)
VCO
(~1.3545 GHz)
÷3
÷ 4 or 5
(is125M)
÷2^PLL4_DIV
CLKout4
÷2^TOF4_ACLK
MUX
TOF4
Frame_in
AFS_div
AFS_mode
Figure 12. PLL4 Block Diagram
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