LMH1983 Datasheet, PDF (41/55 Pages) National Semiconductor (TI) – Generating 44.1 kHz Based highly integrated programmable audio

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LMH1983
SNLS309I – APRIL 2010 – REVISED DECEMBER 2014
9.2.3 A/V Clock Generation Using Free-Run Mode
The LMH1983 can be used in free-run mode, as shown in the following application example. No H_IN, V_IN, and F_IN
input reference timing signals are provided. Instead, the LMH1983 tracks a 27 MHz TCXO reference, which
replaces the external VCXO and loop filter mentioned in previous applications. The LMH1983 can still produce a
specific set of clock output signals required by a downstream endpoint. In this application, LMH1983 PLLs 1-4
provide a 27 MHz, 148.5 MHz, 148.35 MHz, and 98.304 MHz output, respectively.
TCXO
27 MHz
±1ppm
Hin
No input _Vin
Fin
27 MHz
CLKout1
148.5 MHz (PLL2)
CLKout2
LMH1983
148.35 MHz (PLL3)
CLKout3
98.304 MHz
CLKout4
A/V clock
signals will
track the TCXO
and have the
same accuracy
PLL1 Mode = Free run
PLL2 Video Format = 1080p/50
PLL3 Video Format = 1080p/59.94
PLL4 Audio Format = 98.304 MHz with 48 kHz word clock
Figure 30. High-Precision, Stable A/V Clock Generation Using a 27 MHz TCXO Reference
9.2.3.1 Design Requirements
This application requires less components than the previous applications mentioned in this section. This is
because there is no H_IN reference, external VCXO, or loop filter. However, the PLL1 signal is still applied via the
27 MHz TCXO clock signal on the XOin± pins. Using a TCXO for reference allows a stable, standalone clock
generation for PLLs 2-4.
9.2.3.2 Detailed Design Procedure
Since no H_IN input timing signaling is provided, this application example cannot use the "Supported Formats
Lookup Table (LUT)" (see Table 2) for automatic format detection. However, PLLs 2-4 can still be manually
programmed to output the correct output format using Auto Format Detection Codes. To output the desired video
and audio formats from PLLs 2-3, the following output codes should be used:
PLLx
(INPUT/OUTPUT)
PLL2 (Output)
PLL3 (Output)
Table 12. Auto-Format Detection Output Codes for Figure 30
FORMAT CODE
14
13
DESCRIPTION
1080P50
1080P59.94
HSync PERIOD
(in 27 MHz CLOCKS)
480
400.4
To ensure correct auto-detection and the correct CLKout signaling desired in Figure 30, the following SMBus
register values should be verified or changed from their default values.
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