LMH1983 Datasheet, PDF (39/55 Pages) National Semiconductor (TI) – Generating 44.1 kHz Based highly integrated programmable audio

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LMH1983
SNLS309I – APRIL 2010 – REVISED DECEMBER 2014
9.2.2 A/V Clock Generation with Recognized Clock-based Input Reference
The LMH1983 is shown in the following application example where the H_IN input reference timing signal is clock-
based. After achieving genlock, the LMH1983 can produce a specific set of clock output signals required
downstream. In this case, LMH1983 PLLs 1-4 provide a 27 MHz, 74.25 MHz, 74.176 MHz, and 98.304 MHz
output, respectively.
LOOP
FILTER
27 MHz
VCXO
Other clock inputs supported
32, 44.1, 48 or 96 kHz (Audio)
27 MHz (Video)
10 MHz (GPS)
27 MHz
CLKout1
Hin
74.25 MHz (PLL2)
CLKout2
LMH1983
74.176 MHz (PLL3)
CLKout3
A/V clock signals
genlocked to
clock ref. in
98.304 MHz
CLKout4
PLL1 Ref. In Format = Audio word, 27 MHz, or 10 MHz clock
PLL2 Video Format = 1080i/25
PLL3 Video Format = 1080i/29.97
PLL4 Audio Format = 98.304 MHz with 48 kHz word clock
Figure 28. LMH1983 A/V Clock Generation with Non-Format Specific Input Clock Reference
9.2.2.1 Design Requirements
When designing for the LMH1983, it is essential to ensure that the correct VCXO and external loop filter
capacitors are chosen. Refer to VCXO Selection Criteria and Loop Filter Capacitors for guidance regarding how
to select these components to improve timing stability and accuracy.
9.2.2.2 Detailed Design Procedure
Once the appropriate external VCXO and loop filter components are selected, the input timing signaling should
be referenced to the "Supported Formats Lookup Table (LUT)" (see Table 2) to determine whether the video
clock, GPS clock, and audio clock are supported by automatic format detection. From Table 2 and the Auto
Format Detection Codes, all of the reference clock inputs mentioned in this application are supported under the
auto format detection feature. Once PLL1 has genlocked to the chosen H_IN signal, PLLs 2-3 can be set
according to the desired output signals specified in Auto Format Detection Codes. Refer to Table 10 for a list of
possible input and output formats available for auto-format detection in this application. The format code can be
applied as an expected input format for PLL1 (Register 0x20) or a programmed output format for PLL2 (Register
0x07) and PLL3 (Register 0x08).
Table 10. Relevant Auto-Format Detection Codes for Figure 28
PLLx (INPUT/OUTPUT)
PLL2 (Output)
PLL3 (Output)
PLL1 (Input)
PLL1 (Input)
PLL1 (Input)
PLL1 (Input)
PLL1 (Input)
PLL1 (Input)
FORMAT CODE
22
21
25
26
27
28
29
30
DESCRIPTION
1080I25
1080I29.97
48 kHz Audio
96 kHz Audio
44.1 kHz Audio
32 kHz Audio
27 MHz HSync
10 MHz HSync
HSync PERIOD
(in 27 MHz CLOCKS)
960
800.8
562.5
281.25
612.244898
843.75
1
2.7
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