LMH1983 Datasheet, PDF (36/55 Pages) National Semiconductor (TI) – Generating 44.1 kHz Based highly integrated programmable audio

LMH1983
SNLS309I – APRIL 2010 – REVISED DECEMBER 2014
Typical Applications (continued)
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LOOP
FILTER
27 MHz
VCXO
H blank
525i/29.97 digital _{V blank} Hin
blanking pulse inputs
Vin
from FPGA SDI RX F blank Fin
27 MHz
CLKout1
148.5 MHz (PLL2)
CLKout2
LMH1983
148.35 MHz (PLL3)
CLKout3
24.576 MHz
CLKout4
525i/29.97 SDI out
+ embedded audio
HD-SDI Upconverter
(HD/SD Simulcast)
with Audio Embedder
1080i/29.97 SDI out
+ embedded audio
525i/29.97 SDI in
+ embedded audio
PLL1 Ref. In Format = 525i/29.97
PLL2 Video Format = 525i/29.97*
PLL3 Video Format = 1080i/29.97*
PLL4 Audio Format = 24.576 MHz with 48 kHz word clock
* GHQRWHV³3*&/.´PRGH(148.5 or 148.35 MHz)
A/V clock signals
genlocked to SDI in
Figure 23. LMH1983 Video Timing Generation for HD-SDI Up-Conversion with Audio Embed/De-embed
9.2.1.1 Design Requirements
When designing for the LMH1983, it is essential to choose the correct VCXO and external loop filter capacitors.
The following subsections provide guidance regarding how to select these components to improve timing stability
and accuracy.
9.2.1.1.1 VCXO Selection Criteria
The recommended VCXO is CTS part number 357LB3C027M0000, which has an absolute pull range of ±50 ppm
and a temperature range of –20°C to +70°C. A VCXO with a smaller APR can provide better frequency stability
and slightly lower jitter, but the APR must be larger than the anticipated variation of the input frequency range.
9.2.1.1.2 Loop Filter Capacitors
The most common types of capacitors used in many circuits today are ferroelectric ceramic capacitors such as
X7R, Y5V, X5R, Y5U, and so on. These capacitors suffer from piezoelectric effects, which generate an electrical
signal in response to mechanical vibration, stress, and shock. This effect can adversely affect the jitter
performance when presented to the control input to the VCXO. The easiest way to eliminate this effect is to use
tantalum capacitors that do not exhibit the piezoelectric effect.
9.2.1.2 Detailed Design Procedure
Once the appropriate external VCXO and loop filter components are selected, the input timing signaling should
be referenced to Table 2 to determine whether NTSC 525i/29.97 sync format is supported. This video format is a
supported video format for automatic detection under Auto Format Detection Code 0, so it is not necessary to
override the input auto-detection feature.
Once PLL1 has genlocked to the chosen NTSC, 525i input reference signal, PLLs 2-3 can be set according to
the desired output signals specified in Figure 23. Refer to Table 6 and Table 7 for a list of possible input and
output formats available for auto-format detection in Figure 22 and Figure 23, respectively. The format code can
be applied as an expected input format for PLL1 (Register 0x20) or a programmed output format for PLL2
(Register 0x07) and PLL3 (Register 0x08).
PLLx
(INPUT/OUTPUT)
PLL1 (Input)
PLL2 (Output)
PLL3 (Output)
Table 6. Relevant Auto-Format Detection Codes for Figure 22
FORMAT CODE
0
0
13
DESCRIPTION
525I29.97
525I29.97
1080P59.94
HSync PERIOD
(in 27 MHz CLOCKS)
1716
1716
400.4
36
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