LMH1983 Datasheet, PDF (40/55 Pages) National Semiconductor (TI) – Generating 44.1 kHz Based highly integrated programmable audio

LMH1983
SNLS309I – APRIL 2010 – REVISED DECEMBER 2014
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To ensure correct auto-detection and the correct CLKout signaling desired in Figure 28, the following SMBus
register values should be verified or changed from their default values.
REGISTER[Bit(s)]
0x05[5]
0x05[4:3]
0x05[1]
0x07[5:0]
0x08[5:0]
0x11[5:4]
0x11[3:2]
0x12[5:4]
0x13[5:4]
0x14[5:4]
0x2E[4]
0x31[4]
0x34[7:4]
Table 11. SMBus Register Settings for Figure 28
WRITE VALUE
1'b
01'b
0'b
010110'b
010101'b
10'b
01'b
10'b
10'b
10'b
1'b
1'b
0000'b
COMMENTS
Auto Format Detect enabled
PLL1 operating in Genlock mode
Allow PLL2 and PLL3 to use the native clock rates
Set PLL2 Output to Format Detection Code 22 (0x16)
Set PLL3 Output to Format Detection Code 21 (0x15)
Set to always align when misaligned
Drift lock (small misalignment), crash lock (large misalignment)
Set TOF2 to always align when misaligned
Set TOF3 to always align when misaligned
Set AFS_Align_Mode to always align when misaligned
Set PLL2_DIV to divide-by-2 for 74.25 MHz
Set PLL3_DIV to divide-by-2 for 74.176 MHz
Set PLL4_DIV to divide-by-1 for 98.304 MHz
9.2.2.3 Application Curve
10ns / div
Traces 1-4: 1V / div
Figure 29. CLKout 1-4 Signals after Genlock to Clock-Based Reference
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