LMH1983 Datasheet, PDF (4/55 Pages) National Semiconductor (TI) – Generating 44.1 kHz Based highly integrated programmable audio

LMH1983
SNLS309I – APRIL 2010 – REVISED DECEMBER 2014
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Pin Functions (continued)
PIN
I/O
NO.
NAME
13
NO_REF
O
14
15
CLKout4–
CLKout4+
O
16
VDD
–
17
Fout4 (OSCin)
I/O
18
GND
–
19
VDD
–
20
VDD
–
21
GND
–
22
Fout3
O
23
24
CLKout3+
CLKout3–
O
25
Cbyp3
–
26
Cbyp4
–
27
Cbyp2
–
28
29
CLKout2+
CLKout2–
O
30
Fout2
O
31
VDD
–
32
VDD
–
33
34
XOin– ⁽³⁾
XOin+
I
35
36
CLKout1–
CLKout1+
O
37
Fout1
O
38
VDD
–
39
GND
–
40
VC_LPF
O
–
DAP
–
SIGNAL
LEVEL
LVCMOS
LVDS
Power
LVCMOS
GND
Power
Power
GND
LVCMOS
LVDS
Analog
Analog
Analog
LVDS
LVCMOS
Power
Power
LVCMOS/LVDS
LVDS
LVCMOS
Power
GND
Analog
GND
DESCRIPTION
Loss of reference status flag (active high)
Audio clock from PLL4 (fundamental rate is 98.304 MHz).
The output is 24.576 MHz by default and is selectable via the host.
3.3 V supply for CLKout4
Audio frame timing signal for OUT4 (active low.) Timing Generator
fixed to PLL4 clock. The output is the audio-video-frame (AVF) pulse
by default and is programmable via the host. Optional OSCin function
can be used to apply a 27 MHz external clock for PLL4 to generate an
audio clock independent of the video input reference; this function
must be enabled via the host.
Ground
3.3 V supply for PLL3 and PLL4
3.3 V supply for CLKout3
Ground
Video frame timing signal for OUT3 (active low). Timing generator
assignable to PLL1, PLL2, or PLL3. OUT3 format is selectable via the
host.
Video clock from PLL1, PLL2, or PLL3 depending on output
crosspoint mode. The output is 148.35 MHz by default and is
selectable via the host.
Bias bypass for on-chip LDO for PLL3
Connect to 1.0 µF and 0.1 µF bypass capacitors.
Bias bypass for on-chip LDO for PLL4
Connect to 1.0 µF and 0.1 µF bypass capacitors.
Bias bypass for on-chip LDO for PLL2
Connect to 1.0 µF and 0.1 µF bypass capacitors.
Video clock from PLL1, PLL2, or PLL3 depending on output
crosspoint mode. The output is 148.5 MHz by default and is selectable
via the host.
Video frame timing signal for OUT2 (active low). Timing generator
assignable to PLL1, PLL2, or PLL3. OUT2 format is selectable via the
host.
3.3-V supply for CLKout2
3.3-V supply for PLL2
27 MHz VCXO clock signal for PLL1.
– LVCMOS: Directly connect clock signal to XOin+ and bias XOin- to
mid-supply with 0.1µF bypass capacitor.
– LVDS: Directly connect LVDS clock signals to XOin+ and XOin-.⁽⁴⁾
Video clock from PLL1.
The output is 27 MHz by default and is selectable via the host.
Reference frame timing signal for OUT1 (active Low). Timing
generator fixed to PLL1 OUT1 Format follows the reference input
format.
3.3 V supply for CLKout1
Ground
Loop filter for PLL1 charge pump output with VCXO Voltage Control
(VC) sensing.
If free-run and holdover mode, PLL1 is disabled and an internal DAC
outputs a control voltage to the VCXO.
Die Attach Pad (Connect to ground on PCB)
(3) XOin must be driven by a 27 MHz clock in order to read or write registers via I²C.
(4) A TCXO or other clean 27 MHz oscillator can be applied for standalone clock generation using PLLs 2-4 (bypass PLL1).
4
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