LMH1983 Datasheet, PDF (13/55 Pages) National Semiconductor (TI) – Generating 44.1 kHz Based highly integrated programmable audio

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Feature Description (continued)
V in
TOF1
PFD
H in
÷R
PFD
LMH1983
SNLS309I – APRIL 2010 – REVISED DECEMBER 2014
CP
Current
Source
SAR
DAC
MUX
÷N
VCXO
(ext)
Loop Filter
(ext)
÷ 1 or ÷ 2
CLK1 Out
Figure 9. PLL1 Block Diagram
Since PLL2, PLL3, and PLL4 all use PLL1 as their input reference, the performance of PLL1 affects the
performance of all four clock outputs. The loop filters for the other three PLLs are internal, and the bandwidths
are set significantly higher than that of PLL1, so the low frequency jitter characteristics of all four clock outputs
are determined by the loop response of PLL1. Accordingly, special attention should be paid to the PLL1's loop
bandwidth and damping factor.
8.3.2 PLL1 Loop Response Design Equations
The loop response is primarily determined by the loop filter components and the loop gain. A passive second
order loop filter consisting of R_S, C_S, and C_P components can provide sufficient input jitter attenuation for most
applications. In some cases, a higher order filter may be used to shape the low frequency response of PLL1
further. Assuming a topology for the loop filter similar to that shown in the Figure 9, the bandwidth of the PLL is
determined by:
BW_PLL1= R_Sx K_VCO x I_CP1/(2*π*FB_DIV)
where
• R_S is the series resistor value in the external loop filter.
• K_VCO is the nominal 27 MHz VCXO gain in Hz/V. K_VCO= Pull_range*27 MHz/Vin_Range. For the VCXO used in
the typical interface circuit (Mfgr: CTS, P/N 357LB3C027M0000): L_VCO=100 ppm*27 MHz / (3.0V-0.3V) = 1000
Hz/V
• I_CP1 is the current from the PLL1 charge pump.
• FB_DIV is the divide ratio of the PLL, which is set by the R and N register values, this will be equal to the
number of 27 MHz clock pulses in one H_IN period. For NTSC, this value will be 1716.
(1)
Under normal operation, several of these parameters are set by the device automatically, for example the charge
pump current and the value of 'FB_DIV'. When the input reference format changes, both N and the charge pump
current are updated, N is changed to allow for lock to the new reference, and the charge pump current is
adjusted to maintain constant loop bandwidth.
It should be noted that this bandwidth calculation is an approximation and does not take into account the effects
of the damping factor or the second pole introduced by C_P.
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