LMH1983 Datasheet, PDF (35/55 Pages) National Semiconductor (TI) – Generating 44.1 kHz Based highly integrated programmable audio

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9 Applications and Implementation
LMH1983
SNLS309I – APRIL 2010 – REVISED DECEMBER 2014
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LMH1983 is an analog phase locked loop (PLL) clock generator that can output simultaneous clocks at a
variety of video and audio rates, synchronized or “genlocked” to Hsync and Vsync input reference timing. The
LMH1983 features an output Top of Frame (TOF) pulse generator for each of its four channels, each with
programmable timing that can also be synchronized to the reference frame. The clock generator uses a two-
stage PLL architecture to attenuate input timing jitter for minimum jitter transfer. The combination of the external
VCXO, external loop filter, and programmable PLL parameters provides flexibility to optimize the loop bandwidth
and loop response for design applications.
9.2 Typical Applications
9.2.1 Typical Genlock Timing Generation with NTSC 525i/29.97 High Speed Reference
The LMH1983 is commonly used with Hsync, Vsync, and Fsync timing signals as a reference for genlock. Once
these signals are provided, the LMH1983 can produce a specific set of clock output signals required by a
downstream endpoint. In some video applications, a multi-format video sync separator is used to derive the
Hsync, Vsync, and Fsync signals from a standard analog SD/ED/HD video signal. In Figure 22, a LMH1981
multi-format sync separator is used to provide H_IN, V_IN, and F_IN for the LMH1983. In this case, LMH1983 PLLs 1-
4 provide a 27 MHz/29.97 Hz, 148.5 MHz/29.97 Hz, 148.35 MHz/59.94 Hz, and 24.576 MHz/5.994 Hz output,
respectively, to an A/V Frame Synchronizer. Another example of this application can be seen in Figure 23, where
H_IN, V_IN, and F_IN signals are provided directly from an FPGA SDI RX without a sync separator. In the latter
example, the NTSC 525i/29.97 H_IN, V_IN, and F_IN parameters are provided individually for the LMH1983, after
which the LMH1983 provides 3G, 3G/1.001, and Audio Clock Generation.
LOOP
FILTER
27 MHz
VCXO
525i
H sync
Analog
ref. in
LMH1981 _{V sync}
Sync
Hin
Vin
Separator F sync Fin
27 MHz (PLL1)
CLKout1 _{29.97 Hz (TOF1)}
148.5 MHz (PLL2)
CLKout2
29.97 Hz (TOF2)
LMH1983
148.35 MHz (PLL3)
CLKout3
59.94 Hz (TOF3)
24.576 MHz (PLL4)
CLKout4
5.994 Hz
FPGA
A/V Frame Sync with
Downconverter,
Audio Embedder and
De-embedder
525i/29.97 SDI out
+ embedded audio
1080p/59.94 SDI out
+ embedded audio
1080p/59.94 SDI in
+ embedded audio
Genlocked to video ref. in
Figure 22. LMH1983 Video Genlock Timing Generation for A/V Frame Synchronizer
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