LMH1983 Datasheet, PDF (19/55 Pages) National Semiconductor (TI) – Generating 44.1 kHz Based highly integrated programmable audio

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LMH1983
SNLS309I – APRIL 2010 – REVISED DECEMBER 2014
Feature Description (continued)
2^LOA_window x 27 MHz Clock) and when the difference in phase is large (Output > 2^LOA_window x 27 MHz Clock).
Furthermore, if the difference is large, the user can tell the device to achieve alignment either by advancing or
retarding the phase of PLL1. Note that if the difference in alignment is large, achieving alignment via drift lock
may take a very long time (tens of seconds), during which the output clock will not be phase locked to the input
H_IN.
8.3.11 TOF2 and TOF3 Alignment
Similar to TOF1, CLKout2 and CLKout3 have associated video formats. The format is determined by
programming Register 0x07 and 0x08, respectively. Once the format is programmed and the TOF outputs are
enabled, a TOF pulse is generated at the appropriate rate for each of the outputs. There are four different
alignment modes that may be selected for TOF2 and TOF3:
Table 1. TOF2/TOF3 Alignment Modes
TOF2/TOF3 ALIGNMENT MODE
0
1
2
3
DESCRIPTION
Auto Align when Misaligned
One Shot Manual Align
Always Align
Never Align
TOF2 and TOF3 are generally aligned with TOF1. The alignment status bit will only be set if the frame rates are
the same as one another. Another option for alignment is via software, where the TOFX_INIT bit is set. For
example, the LSB of Register 0x12 is the TOF2_INIT bit. Writing a 1 to this bit while also setting TOF2 alignment
mode to anything other than 3 (Never Align) will cause TOF2 to reset its phase immediately. Note that this bit is
a self-clearing bit, so it will always return a zero.
8.3.11.1 TOF3 Initialization Set Up
Under some circumstances, it is possible for an LMH1983 to power up in an anomalous state in which the output
of PLL3 exhibits a large amount of cycle-to-cycle jitter. A simple register write after power up will prevent the
device from remaining in this state. Writing to Register 0x13[5:4] = 10'b to force Always Align Mode ensures that
the device will not exhibit poor duty cycle performance on CLKout3.
8.3.12 TOF4 Alignment
CLKout4 of the LMH1983 is most often used to generate an audio clock. The default base audio clock rate is 48
kHz, and this sample clock is synchronous in phase with the video frame only once every 5 frames for 29.97 and
30 Hz frame rate standards, or once every ten frames for 60 Hz and 59.94 Hz systems. The LMH1983 can
generate a TOF4 pulse that occurs at this rate, allowing audio frames to be synchronized with the video frames.
TOF4 may be aligned either to TOF1 or to the F_IN input. Additionally, there is an external INIT input that can be
used to set TOF4 alignment.
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