LMH1983 Datasheet, PDF (29/55 Pages) National Semiconductor (TI) – Generating 44.1 kHz Based highly integrated programmable audio

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LMH1983
SNLS309I – APRIL 2010 – REVISED DECEMBER 2014
Register Map (continued)
ADD NAME
0x14 Alignment Control – AFS
0x15 Loss of Alignment Control
0x16
LOR Control – Holdover
Sampled Voltage MSB
0x17
LOR Control – Holdover
Sampled Voltage LSB
0x18
LOR Control Free-run
Control Voltage MSB
0x19
LOR Control – Free-run
Control Voltage LSB
0x1A
LOR Control – ADC and
DAC Disable
Table 3. LMH1983 Register Map (continued)
BITS FIELD
7:6 RSVD
5:4 AFS_Align_Mode
3
AFS_Init_Input
2:1 RSVD
0
AFS_INIT
7:3 RSVD
2:0 LOA_Window
7:2 RSVD
1:0 VC_Hold_MSB
7:0 VC_Hold_LSB
7:2 RSVD
1:0 VC_Free_MSB
7:0 VC_Free_LSB
7:2 RSVD
1
ADC_Disable
0
DAC_Disable
R/W DEFAULT
DESCRIPTION
00
Reserved
00 = auto align when misaligned
01 = one shot manual align. AFS_Init_Input reg determines if
R/W
11
done by pin (INIT) or register (AFS_INIT = 1)
10 = always align
11= never align
0 = Rising edges on INIT (pin 6) trigger AFS one shot manual
R/W
0
align.
1 = Writing ‘1’ to AFS_Init register triggers AFS one shot
manual align.
00
Reserved
Writing one to this bit while also writing AFS_Align_Mode = 3
and AFS_Init_Input=1, or providing a rising edge on the init
input when AFS_Align_Mode ≠ 3 and AFS_Init_Input=0, will
cause the AFS_INIT output to go high for at least one vframe
R/W
0
period + one Hsync period and not more than one vframe
period + two Hsync periods. The assertion of AFS_INIT must
happen immediately (it cannot wait for Hsync). If
AFS_Align_Mode = 3, toggling the init input will have no effect.
This bit is self-clearing and will always read zero.
00000 Reserved
Number of 27 MHz clocks between the TOF1 and Vsync
before Loss of Alignment is reported.
R/W
010
If the code loaded in this register is n, then Loss of Alignment
will be reported if the difference between TOF1 and Vsync
exceeds 2ⁿ 27 MHz clock cycles
000000 Reserved
The VC_Hold[9:0] input signal changes rather slowly. For
synchronization, it should be sampled on consecutive 27 MHz
clocks until two identical values are found. This value will be
saved as VC_Hold_sampled[9:0].
R
10
Whenever the VC_Hold[9:8] register is read,
VC_Hold_sampled[9:8] is returned, and VC_Hold[7:0] will
memorize the current value of VC_Hold_sampled[7:0] (to be
read at a later time).
This scheme allows a coherent 10-bit value to be read.
Returns a synchronized snapshot of the VC_Hold[9:8] (MSB).
The VC_Hold[9:0] input signal changes rather slowly. For
synchronization, it should be sampled on consecutive 27 MHz
clocks until two identical values are found. This value will be
saved as VC_Hold_sampled[9:0].
R
—
Whenever the VC_Hold[9:8] register is read,
VC_Hold_sampled[9:8] is returned, and VC_Hold[7:0] will
memorize the current value of VC_Hold_sampled[7:0] (to be
read at a later time).
This scheme allows a coherent 10-bit value to be read.
Returns a synchronized snapshot of the VC_Hold[7:0] (LSB)
Reserved
Free-run Control Voltage (VC_Free[9:0]) is the voltage
R/W
01
asserted on VC_LPF pin in free-run mode.
Writing will change the MSB (VC_Free[9:8])
Free-run Control Voltage (VC_Free[9:0]) is the voltage
R/W
0xFF asserted on VC_LPF pin in free-run mode.
Writing will change the LSB (VC_Free[7:0])
000000 Reserved
Directly controls the ADC_Disable output port.
R/W
0
0 = enable holdover ADC
1 = disable holdover ADC
Directly controls the DAC_Disable output port.
R/W
0
0 = enable Free-run/Holdover DAC
1 = disable Free-run/Holdover DAC
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