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LMH1983 Datasheet, PDF (25/55 Pages) National Semiconductor (TI) – Generating 44.1 kHz Based highly integrated programmable audio
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LMH1983
SNLS309I – APRIL 2010 – REVISED DECEMBER 2014
Programming (continued)
8.5.3 Read Sequence
Read sequences consist of two I2C transfers. The first is the address access transfer, which consists of a write
sequence that transfers only the address to be accessed. The second is the data read transfer which starts at
the address indicated in the first transfer and increments to the next address, continuing to read addresses until
a stop condition is encountered. The timing diagram of the address access transfer is shown in Figure 20. A read
sequence begins with a start pulse, the slave device address including the Read/Write bit (Read = 1'b and Write
= 0'b), and then its ACK bit. The next byte is the address to be read, followed by the ACK bit and the stop bit to
indicate the end of the address access transfer. The subsequent read data transfer shown consists of the start
pulse, the slave device address including the Read/Write bit (this time a R/W Bit = 1'b, indicating that the data is
to be read) and the ACK bit. The next byte is the data read from the initial access address. After each data byte
is read, the address is incremented, thereby allowing the next byte of data to be read from the subsequent
address of the device. Each byte is separated from the previous byte by an ACK bit, and the end of the read
sequence is indicated with a STOP bit. The timing diagram for a read data transfer is shown in Figure 21 for
additional timing details.
SCL
SDA
A7 A6 A5 A4 A3 A2 A1 A0
S 110011000
t
a
r
I2C
WA
rC
t
Slave
IK
Address
t
$CC
e
Address
0S
t
Ao
Cp
K
Figure 20. Read Sequence — Address Access Transfer
SCL
SDA
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
S 110011010
0
0S
t
t
a
r
I2C
RA
eC
Data Byte 1
A
C
Data Byte n
Ao
Cp
t
Slave
aK
K
K
Address
d
$CD
Figure 21. Read Sequence — Data Read Transfer
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