LMH1983 Datasheet, PDF (3/55 Pages) National Semiconductor (TI) – Generating 44.1 kHz Based highly integrated programmable audio

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LMH1983
SNLS309I – APRIL 2010 – REVISED DECEMBER 2014
5 Description (continued)
When locked to reference, an internal 10-bit ADC will track the loop filter control voltage. When a loss of
reference (LOR) occurs, the LMH1983 can be programmed to hold the control voltage to maintain output
accuracy within ±0.5 ppm (typical) of the previous reference. The LMH1983 can be configured to re-synchronize
to a previous reference with glitch-less operation.
6 Pin Configurations and Functions
RTA40A Package
40-Pin WQFN Package with Exposed Thermal Pad
Top View
VDD 1
VDD 2
Hin 3
Vin 4
Fin 5
INIT 6
ADDR 7
SDA 8
SCL 9
VDD 10
Die Attach Pad (DAP)
Connect to GND on PCB
30 Fout2
29 CLKout2-
28 CLKout2+
27 Cbyp2
26 Cbyp4
25 Cbyp3
24 CLKout3-
23 CLKout3+
22 Fout3
21 GND
PIN
I/O
NO.
NAME
1
VDD
–
2
VDD
–
3
Hin
I
4
Vin
I
5
Fin
I
6
INIT
I
7
ADDR
I
8
SDA ⁽¹⁾
I/O
9
SCL ⁽¹⁾
I
10
VDD
–
11
NO_LOCK ⁽²⁾
O
12
NO_ALIGN
O
Pin Functions
SIGNAL
LEVEL
DESCRIPTION
Power
Power
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
I²C
I²C
Power
LVCMOS
LVCMOS
3.3-V supply for PLL1
3.3-V supply for logic I/O
Horizontal sync reference signal
Auto polarity correction for HVF will be based off Hin polarity.
Recognized clock inputs can be applied to Hin.
Vertical sync reference signal
Field sync (odd/even) reference signal
Reset signal for audio-video phase alignment (rising edge triggered)
I²C address select
Pin settings:
– Tie low: 0x65 (7-bit slave address in hex)
– Float: 0x66
– Tie high: 0x67
I²C Data signal
I²C Clock signal
3.3-V supply for logic I/O
Loss of lock status flag for PLLs 1-4 (active high)
Loss of alignment status flag for OUTs 1–4 (active high)
(1) SDA and SCL pins each require a pull-up resistor of 4.7 kΩ to the VDD supply.
(2) The NO_LOCK status flag is derived from the Lock Status register bits (LOCK1-4) for each PLL. Each lock status bit can be masked
from the NO_LOCK flag by setting their respective mask bits.
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