LMH1983 Datasheet, PDF (24/55 Pages) National Semiconductor (TI) – Generating 44.1 kHz Based highly integrated programmable audio

LMH1983
SNLS309I – APRIL 2010 – REVISED DECEMBER 2014
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8.4.4 Free-Run, Genlock, and Holdover Modes
The LMH1983 primary PLL can operate in three different modes, selected via Register 0x05. These modes are
Free-run, Genlock, and Holdover Mode:
• Free-run mode: H_IN, V_IN, and F_IN are not used, and the VCXO control voltage is set by the contents of
Registers 0x18 and 0x19. By writing to these registers, the VCXO voltage can be trimmed up or down. The
slave PLLs will remain locked to the primary PLL.
• Genlock mode: The VCXO control voltage is actively controlled to maintain lock between H_IN and the VCXO
output frequency. In addition, there is a second PLL loop that may take over to assert a lock between TOF1
and F_IN. See TOF1 Alignment for more details.
• Holdover mode: In the event that the reference is lost, there is an A/D — D/A pair that is able to take over for
the PLL control loop and hold the VCXO control voltage constant. For this to work properly, the device must
realize that it has lost its reference shortly after the reference is actually lost. Some sync separators, when the
analog input is lost, will output random pulses from the H, V, and F outputs. This can confuse the device.
Therefore if Holdover mode is to be used in conjunction with an analog sync separator, it is best to gate the
H, V, and F signals with a signal that indicates if there is a valid reference input.
8.5 Programming
8.5.1 I²C Interface Protocol
The protocol of the I²C interface begins with the start pulse, followed by a byte which consists of a seven-bit
slave device address and a Read/Write bit as an LSB. The default address of the LMH1983 for write sequences
is 0xCC (11001100'b) and for read sequences is 0xCD (11001101'b). The base address can be changed with the
ADDR pin. When ADDR is left open, the base address is 0x66 (which, when left shifted for a write sequence
becomes 0xCC). When ADDR is connected to GND, the base address is 0x65, and when ADDR is connected to
V_DD, the base address is 0x67.
Please note: The I2C interface of the LMH1983 requires the 27 MHz VCXO clock input to be running in order to
read I2C data packets into the 27 MHz clock domain. If the 27 MHz clock is not running, the I2C interface should
still respond (ACK), but Write commands may be ignored and Read commands may return invalid data.
8.5.2 Write Sequence
The write sequence begins with a start condition, which consists of the master pulling SDA low while SCL is high.
The slave address is sent next. The slave address is a seven-bit address followed by the Read/Write bit (Read =
1'b and Write = 0'b). For the default base address of 0x66 (1100110'b), the 0 is appended to the end, and the net
address is 0xCC. Each byte sent after the address is followed by an ACK bit. When SCL is high, the master will
release the SDA line, and the slave pulls SDA low to acknowledge. Once the device address has been sent, the
next byte sent is the register address. Following the register address and the ACK, the data byte is sent. When
more than one data byte is sent, the register address is automatically incremented so that the data is written into
the next address location. The Write Sequence Timing Diagram is shown in Figure 19. Note that there is an ACK
bit following each data byte.
SCL
SDA
A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
S ^110011000
t
a
r
I²C
RA
eC
t
Slave
aK
Address
d
$CD
Address
0
0
0S
t
A
C
Data Byte 1
A
C
Data Byte n
Ao
Cp
K
K
K
Figure 19. Write Sequence Timing Diagram
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