LMH1983 Datasheet, PDF (14/55 Pages) National Semiconductor (TI) – Generating 44.1 kHz Based highly integrated programmable audio

LMH1983
SNLS309I – APRIL 2010 – REVISED DECEMBER 2014
Feature Description (continued)
VC_LPF
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CS
CP
RS
Figure 10. External Loop Filter Schematic Detail
At frequencies far above the –3dB loop bandwidth, the closed-loop frequency response of PLL1 will roll off at
about –40dB/decade, which is useful for attenuating input jitter at frequencies above the loop bandwidth. Near
the –3dB corner frequency, the roll-off characteristic depends on other factors, such as damping factor and filter
order.
To prevent output jitter due to the modulation of the VCXO by the PLL's phase comparison frequency, the
bandwidth needs to meet the following criterion:
BW ≤ (27 MHz / FB_DIV ) / 20
(2)
PLL1's damping factor can be approximated by:
DF = (R_S/2)√(I_CP1 x C_S x K_VCO/FB_DIV)
where
• C_S is the value of the series capacitor (in Farads)
(3)
Typically, DF is targeted to be between 1/√2 and 1, which will yield a good trade-off between lock time and
reference spur attenuation. DF is related to the phase margin, a measure of the PLL stability.
There is a second parallel capacitor, C_P, which is needed to filter the reference spurs introduced by the PLL. The
spurs may modulate the VCXO control voltage, leading to jitter. The following relationship should be used to
determine C_P:
C_P ≈ C_S/20
(4)
The PLL loop gain, K, can be calculated as:
K = I_CP1 x K_VCO/FB_DIV
(5)
Therefore, Bandwidth and Damping Factor can be expressed in terms of K:
BW = R_S x K
(6)
DF = (R_S/2) x √(C_S x K)
(7)
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