DS90UB914A-Q1 Datasheet, PDF (51/61 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Deserializer

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9.2.2.3 Application Curves
DS90UB914A-Q1
SNLS499A – APRIL 2016 – REVISED JUNE 2016
Time (200 ps/DIV)
Figure 38. STP Eye Diagram at 1.4-Gbps Line Rate (100-
MHz Pixel Clock) from Deserializer CML Loop-through
Output (CMLOUT±)
Time (2.5 ns/DIV)
Figure 39. STP Eye Diagram with 100-MHz TX Pixel Clock
Overlay from Deserializer CML Loop-through Output
(CMLOUT±)
10 Power Supply Recommendations
This device is designed to operate from an input core voltage supply of 1.8 V. Some devices provide separate
power and ground terminals for different portions of the circuit. This is done to isolate switching noise effects
between different sections of the circuit. Separate planes on the PCB are typically not required. Terminal
description tables typically provide guidance on which circuit blocks are connected to which power terminal pairs.
In some cases, an external filter may be used to provide clean power to sensitive circuits such as PLLs. The
voltage applied on V_DDIO (1.8V, 3.3V) or other power supplies making up V_{DD_n} (1.8V) should be at the input pin -
any board level DC drop should be compensated (i.e. ferrite beads in the path of the power supply rails).
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