DS90UB914A-Q1 Datasheet, PDF (15/61 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Deserializer

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PDB= H
DS90UB914A-Q1
SNLS499A – APRIL 2016 – REVISED JUNE 2016
OEN
VIH
OSS_SEL
RIN
(Diff.)
t_ONS
LOCK TRI-_TST_RA_IT_-SE _TATE
VIH
t_SES
LOW
PASS
HIGH
ROUT[0:11],
HS, VS
TRI-STATE
PCLK
(RFB = L)
TRI-STATE
LOW
LOW
VIL
HIGH
ACTIVE
ACTIVE
ACTIVE
VIL
t_ONH
t_SEH
LOW
'RQ¶W &DUH
TRI-STATE
HIGH
LOW
TRI-STATE
LOW
TRI-STATE
Figure 9. Output State (Setup and Hold) Times
Frequency
F_PCLK+
fdev (max)
fdev F_PCLK
F_PCLK-
1 / fmod
fdev (min)
Time
Figure 10. Spread Spectrum Clock Output Profile
7.8 Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN / FREQ
MIN
10-bit mode
50 MHz – 100 MHz
10
t_RCP
Receiver Output
Clock Period⁽¹⁾
12-bit high frequency mode
37.5 MHz - 75MHz
PCLK (Figure 7)
13.33
12-bit low frequency mode
25 MHz - 50MHz
20
10-bit mode
50 MHz – 100 MHz
45%
t_PDC
PCLK Duty Cycle
12-bit high frequency mode
37.5 MHz - 75MHz
PCLK
40%
12-bit low frequency mode
25 MHz - 50MHz
40%
NOM
T
MAX
20
UNIT
T 26.67
ns
T
40
50% 55%
50% 60%
50% 60%
(1) T is the period of the PCLK.
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