DS90UB914A-Q1 Datasheet, PDF (1/61 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Deserializer

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DS90UB914A-Q1
SNLS499A – APRIL 2016 – REVISED JUNE 2016
DS90UB914A-Q1 25-MHz to 100-MHz 10/12-Bit FPD-Link III Deserializer
1 Features
•1 Qualified for Automotive Applications AEC-Q100
– Device Temperature Grade 2: –40℃ to +105℃
Ambient Operating Temperature Range
– Device HBM ESD Classification Level ±8kV
– Device CDM ESD Classification Level C6
• 25-MHz to 100-MHz Input Pixel Clock Support
• Programmable Data Payload:
– 10-bit Payload up to 100 MHz
– 12-bit Payload up to 75 MHz
• Continuous Low Latency Bidirectional Control
Interface Channel with I2C Support at 400 kHz
• 2:1 Multiplexer to choose between two input
images
• Capable of Receiving over 15m Coaxial or 20m
Shielded Twisted-pair Cables
• Robust Power-Over-Coaxial (PoC) Operation
• Receive Equalizer Automatically Adapts for
Changes in Cable Loss
• LOCK Output Reporting Pin and @SPEED BIST
Diagnosis Feature to Validate Link Integrity
• Single Power Supply at 1.8 V
• ISO 10605 and IEC 61000-4-2 ESD Compliant
• EMI/EMC Mitigation with Programmable Spread
Spectrum (SSCG) and Receiver Staggered
Outputs
2 Applications
• Automotive
– Surround View Systems (SVS)
– Rear and Front View Cameras
– Driver Monitor Cameras (DMS)
– Remote Satellite RADAR Sensors
• Security and Surveillance
• Industrial Machine Vision
3 Description
The DS90UB914A-Q1 device offers an FPD-Link III
interface with a high-speed forward channel and a
bidirectional control channel for data transmission
over a single coaxial cable or differential pair. The
DS90UB914A-Q1 device incorporates differential
signaling on both the high-speed forward channel and
bidirectional control channel data paths. The
deserializer is targeted for connections between
imagers and video processors in an ECU (Electronic
Control Unit). This device is ideally suited for driving
video data requiring up to 12-bit pixel depth plus two
synchronization signals along with bidirectional
control channel bus.
The deserializer features a multiplexer to allow
selection between two input imagers, one active at a
time. The primary video transport converts 10-bit or
12-bit data to a single high-speed serial stream, along
with a separate low latency bidirectional control
channel transport that accepts control information
from an I2C port and is independent of video blanking
period.
Using TI’s embedded clock technology allows
transparent full-duplex communication over a single
differential pair, carrying asymmetrical-bidirectional
control channel information. This single serial stream
simplifies transferring a wide data bus over PCB
traces and cable by eliminating the skew problems
between parallel data and clock paths. This
significantly saves system cost by narrowing data
paths that in turn reduce PCB layers, cable width,
and connector size and pins. In addition, the
Deserializer inputs provide adaptive equalization to
compensate for loss from the media over longer
distances. Internal DC-balanced encoding/decoding is
used to support AC-coupled interconnects.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DS90UB914A-Q1 WQFN (48)
7.00 mm x 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Parallel
Data In
10 or 12
Simplified Schematic
FPD-Link III
Parallel
Data Out
10 or 12
Megapixel
Imager/Sensor
2
HSYNC,
VSYNC
4
GPO
2
DS90UB913A-
Q1
Bidirectional
Control Bus Serializer
Bidirectional
Control Channel
DS90UB914A-
Q1
Deserializer
2
HSYNC,
VSYNC
4
GPIO
2
Bidirectional
Control Bus
DSP, FPGA/
µ -Processor/
ECU
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.