DS90UB914A-Q1 Datasheet, PDF (22/61 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Deserializer

DS90UB914A-Q1
SNLS499A – APRIL 2016 – REVISED JUNE 2016
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Feature Description (continued)
8.3.7 LVCMOS V_DDIO Option
1.8-V/3.3-V Deserializer outputs are user configurable to provide compatibility with 1.8-V and 3.3-V system
interfaces.
8.3.8 EMI Reduction
8.3.8.1 Deserializer Staggered Output
The receiver staggers output switching to provide a random distribution of transitions within a defined window.
Outputs transitions are distributed randomly. This minimizes the number of outputs switching simultaneously and
helps to reduce supply noise. In addition it spreads the noise spectrum out reducing overall EMI.
8.3.8.2 Spread Spectrum Clock Generation (SSCG) on the Deserializer
The DS90UB914A-Q1 parallel data and clock outputs have programmable SSCG ranges from 25 MHz to 100
MHz. The modulation rate and modulation frequency variation of output spread is controlled through the SSCG
control registers on the DS90UB914A-Q1 device. SSCG profiles can be generated using bits [3:0] in register
0x02 on the Deserializer.
8.3.9 Pixel Clock Edge Select (TRFB / RRFB)
The TRFB/RRFB selects which edge of the Pixel Clock is used. For the SER, this register determines the edge
that the data is latched on. If TRFB register is 1, data is latched on the Rising edge of the PCLK. If TRFB register
is 0, data is latched on the Falling edge of the PCLK. For the DES, this register determines the edge that the
data is strobed on. If RRFB register is 1, data is strobed on the Rising edge of the PCLK. If RRFB register is 0,
data is strobed on the falling edge of the PCLK.
PCLK
DIN/
ROUT
TRFB/RRFB: 0
TRFB/RRFB: 1
Figure 15. Programmable PCLK Strobe Select
8.3.10 Power Down
The DES has a PDB input pin to ENABLE or power down the device. Enabling PDB on the DES will disable the
link to save power. If PDB = HIGH, the DES locks to the input stream and assert the LOCK pin (HIGH) and
output valid data. When PDB = LOW, all outputs are in TRI-STATE. Please refer to Power-Up Requirements and
PDB Pin for power-up requirements.
8.4 Device Functional Modes
8.4.1 DS90UB913A/914A Operation with External Oscillator as Reference Clock
In some applications, the pixel clock that comes from the imager can have jitter which exceeds the tolerance of
the DS90UB913A/914A chipsets. In this case, the DS90UB913A-Q1 device should be operated by using an
external clock source as the reference clock for the DS90UB913A/914A chipsets. This is the recommended
operating mode. The external oscillator clock output goes through a divide-by-2 circuit in the DS90UB913A-Q1
Serializer and this divided clock output is used as the reference clock for the imager. The output data and pixel
clock from the imager are then fed into the DS90UB913A-Q1 device. Figure 16 shows the operation of the
DS90UB13A/914A chipsets while using an external automotive grade oscillator.
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