DS90UB914A-Q1 Datasheet, PDF (25/61 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Deserializer

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DS90UB914A-Q1
SNLS499A – APRIL 2016 – REVISED JUNE 2016
Device Functional Modes (continued)
8.4.3 MODE Pin on Deserializer
The MODE pin on the Deserializer can be used to configure the device to work in the 12-bit low-frequency mode,
12-bit high-frequency mode, or the 10-bit mode of operation. Internally, the DS90UB913A/914A chipset operates
in a divide-by-1 mode in the 12-bit low-frequency mode, divide-by-2 mode in the 10-bit mode and a divide-by-1.5
mode in the 12-bit high frequency mode. The pin must be pulled to V_DD (1.8 V, not V_DDIO) with a 10-kΩ resistor
and a pull-down resistor R_MODE of the recommended value to set the different modes in the Deserializer as
mentioned in Table 1. The Deserializer automatically configures the Serializer to correct mode via the back-
channel. The recommended maximum resistor tolerance is 1%.
.
1.8 V
10 k
MODE
R_MODE
Deserializer
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Figure 18. Mode Pin Configuration on DS90UB914A-Q1 Deserializer
Table 1. DS90UB914A-Q1 Deserializer MODE Resistor Value
DS90UB914A-Q1 DESERIALIZER MODE RESISTOR VALUE
MODE SELECT
12-bit low frequency mode 25-50 MHz PCLK, 10/12-bits DATA+ 2 SYNC.
Note: No HS/VS restrictions (raw).
R_MODE RESISTOR VALUE (kΩ)
0
12-bit high frequency mode 37.5-75 MHz PCLK, 10/12-bits DATA+ 2 SYNC.
Note: No HS/VS restrictions (raw).
3
10-bit mode 50–100 MHz PCLK, 10-bits DATA+ 2 SYNC.
Note: HS/VS restricted to no more than one transition per 10 PCLK cycles.
11
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