DS90UB914A-Q1 Datasheet, PDF (16/61 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Deserializer

DS90UB914A-Q1
SNLS499A – APRIL 2016 – REVISED JUNE 2016
Deserializer Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN / FREQ
MIN
t_CLH
t_CHL
LVCMOS Low-to-
High Transition Time
V_DDIO: 1.71 V to 1.89 V or 3 V
to 3.6 V, C_L = 8 pF
LVCMOS High-to-
Low Transition Time
(lumped load)
Default Registers (Figure 5)⁽²⁾
PCLK
1.3
1.3
t_CLH
t_CHL
LVCMOS Low-to-
High Transition Time
V_DDIO: 1.71 V to 1.89 V or 3 V
to 3.6 V, C_L = 8 pF
LVCMOS High-to-
Low Transition Time
(lumped load)
Default Registers (Figure 5)⁽²⁾
ROUT[11:0], HS, VS
1
1
t_ROS
t_ROH
ROUT Setup
Data to PCLK ⁽¹⁾
ROUT Hold
Data to PCLK ⁽¹⁾
V_DDIO: 1.71 V to 1.89 V or 3 V
to 3.6 V, C_L = 8 pF (lumped
load), Default Registers
(Figure 7)
ROUT[11:0], HS, VS
0.38T
0.38T
10–bit mode
50 - 100 MHz
154T
t_DD
Deserializer Delay⁽¹⁾
Default Registers
Register 0x03h b[0] (RRFB = 1)
(Figure 6)⁽²⁾
12–bit low frequency
mode
25 - 50 MHz
12–bit high frequency
mode
37.5 - 75 MHz
109T
73T
10–bit mode
50 - 100 MHz
t_DDLT
Deserializer Data
Lock Time
With Adaptive Equalization
(Figure 4)
12–bit low frequency
mode
25 - 50 MHz
12–bit high frequency
mode
37.5 - 75 MHz
10–bit mode
PCLK = 100 MHz
t_RCJ
Receiver Clock Jitter
PCLK
SSCG[3:0] = OFF ⁽²⁾
12–bit low frequency
mode, PCLK = 50 MHz
12–bit high frequency
mode, PCLK = 75 MHz
10–bit mode
PCLK = 100 MHz
t_DPJ
Deserializer Period PCLK
Jitter
SSCG[3:0] = OFF ^{(2) (3)}
12–bit low frequency
mode, PCLK = 50 MHz
12–bit high frequency
mode, PCLK = 75 MHz
10–bit mode
PCLK = 100 MHz
t_DCCJ
Deserializer Cycle- PCLK
to-Cycle Clock Jitter SSCG[3:0] = OFF^{(2) (4)}
12–bit low frequency
mode, PCLK = 50 MHz
12–bit high frequency
mode, PCLK = 75 MHz
Spread Spectrum
f_dev
Clocking Deviation
25 MHz – 100 MHz
Frequency
LVCMOS Output Bus
Spread Spectrum ^{SSC[3:0] = ON (Figure 10)(2)}
f_mod
Clocking Modulation
Frequency
25 MHz – 100 MHz
NOM
2
2
2.5
2.5
0.5T
0.5T
15
15
15
20
22
45
170
180
300
440
460
565
±0.5% to
±1.5%
5 to 50
(2) Specification is verified by characterization and is not tested in production.
(3) t_DPJ is the maximum amount of jitter measured over 30,000 samples based on Time Interval Error (TIE).
(4) t_DCCJ is the maximum amount of jitter between adjacent clock cycles measured over 30,000 samples.
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MAX
2.8
2.8
UNIT
ns
4
ns
4
ns
158T
112T
ns
75T
22
22
ms
22
30
35
ps
90
815
330
ps
515
1760
730
ps
985
kHz
16
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