DS90UB914A-Q1 Datasheet, PDF (13/61 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Deserializer

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DS90UB914A-Q1
SNLS499A – APRIL 2016 – REVISED JUNE 2016
7.7 Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C-Compatible⁽¹⁾
Over recommended supply and temperature ranges unless otherwise specified
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX UNIT
RECOMMENDED INPUT TIMING REQUIREMENTS
V_IH
V_IL
V_HY
V_OL
I_IN
t_R
t_F
t_SU;DAT
t_HD;DAT
t_SP
C_IN
Input High Level
Input Low Level
Input Hysteresis
Output Low Level⁽²⁾
Input Current
SDA Rise Time-READ
SDA Fall Time-READ
SDA and SCL
SDA and SCL
0.7*V_DDIO
GND
SDA, V_DDIO = 1.8V, I_OL= 0.9 mA
0
SDA, V_DDIO = 3.3V, I_OL= 1.6 mA
0
SDA or SCL, V_IN= V_DDIO OR GND
−10
SDA, RPU = 10 kΩ, Cb ≤ 400 pF
(Figure 1)
(See Figure 1)
(See Figure 1)
SDA or SCL
V_DDIO
V
0.3*V_DDIO
V
>50
mV
0.36
V
0.4
10 µA
430
ns
20
ns
560
ns
615
ns
50
ns
<5
pF
(1) Specification is verified by design.
(2) FPD-Link device was designed primarily for point-to-point operation and a small number of attached slave devices. As such the
Minimum I_OL pullup current is targeted to lower value than the minimum I_OL in the I2C specification.
SDA
t_f
SCL
START
t_LOW
t_r
t_f
t_HD;STA
t_BUF
t_r
t_HD;STA
t_HD;DAT
t_HIGH
t_SU;DAT
t_SU;STA
t_SU;STO
REPEATED
START
Figure 1. Bi-directional Control Bus Timing
STOP START
Device Pin Name
PCLK
(RFB = H)
Signal Pattern
T
D_IN/R_OUT
Figure 2. “Worst Case” Test Pattern for Power Consumption
Single Ended
R_{IN+ or} R_IN-
V_IN
V_IN
0V
Differential
(RIN+) - (RIN-)
V_ID
0V
Figure 3. Deserializer VID Diagram
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