DS90UB914A-Q1 Datasheet, PDF (19/61 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Deserializer

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DS90UB914A-Q1
SNLS499A – APRIL 2016 – REVISED JUNE 2016
8.3 Feature Description
8.3.1 Serial Frame Format
The High Speed Forward Channel is composed of 28 bits of data containing video data, sync signals, I2C and
parity bits. This data payload is optimized for signal transmission over an AC-coupled link. Data is randomized,
balanced and scrambled. The 28-bit frame structure changes in the 12-bit low frequency mode, 12-bit high
frequency mode and the 10-bit mode internally and is seamless to the customer. The bidirectional control
channel data is transferred over the single serial link along with the high-speed forward data. This architecture
provides a full duplex low speed forward and backward path across the serial link together with a high speed
forward channel without the dependence on the video blanking phase.
8.3.2 Line Rate Calculations for the DS90UB913A/914A
The DS90UB913A-Q1 device divides the clock internally by divide-by-1 in the 12-bit low frequency mode, by
divide-by-2 in the 10-bit mode and by divide-by-1.5 in the 12-bit high frequency mode. Conversely, the
DS90UB914A-Q1 multiplies the recovered serial clock to generate the proper pixel clock output frequency. Thus
the maximum line rate in the three different modes remains 1.4 Gbps. The following are the formulae used to
calculate the maximum line rate in the different modes:
• For the 12-bit low frequency mode, Line rate = f_PCLK*28; for example, f_PCLK = 50 MHz, line rate = 50*28 = 1.4
Gbps
• For the 12-bit high frequency mode, Line rate = f_PCLK*(2/3)*28; for example, f_PCLK = 75 MHz, line rate =
(75)*(2/3)*28 = 1.4 Gbps
• For the 10-bit mode, Line rate = f_PCLK/2*28; for example, f_PCLK = 100 MHz, line rate = (100/2)*28 = 1.4 Gbps
8.3.3 Deserializer Multiplexer Input
The DS90UB914A-Q1 offers a 2:1 multiplexer that can be used to select which camera is used as the input.
Figure 12 shows the operation of the 2:1 multiplexer in the Deserializer. The selection of the camera can be pin
controlled as well as register controlled. Both the Deserializer inputs cannot be enabled at the same time. If the
Serializer A is selected as the active Serializer, the back-channel for Deserializer A turns ON and vice versa. To
switch between the two cameras, first the Serializer B has to be selected using the SEL pin/register on the
Deserializer. After that the back channel driver for Deserializer B has to be enabled using the register in the
Deserializer.
Camera A
CMOS
Image
Sensor
DATA
PCLK
Serializer A
FSYNC
Deserializer
DATA
PCLK
FSYNC
I²C
I2C
Camera B
CMOS
Image
Sensor
DATA
PCLK
Serializer B
FSYNC
I²C
ECU
Module
PC
Copyright © 2016, Texas Instruments Incorporated
Figure 12. Using the Multiplexer on the Deserializer to Enable a Two-Camera System
Copyright © 2016, Texas Instruments Incorporated
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