DS90UB914A-Q1 Datasheet, PDF (48/61 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Deserializer

DS90UB914A-Q1
SNLS499A – APRIL 2016 – REVISED JUNE 2016
9.2.1.2 Detailed Design Procedure
Figure 33 shows a typical connection using a Coax interface to the DS90UB914A-Q1 Deserializer.
1.8 V
DS90UB914A-Q1
VDDIO
VDDD
C3
C11
VDDIO1
C8 C16
C18
VDDR
C4
C12
VDDIO2
C9
1.8 V
FB1
1.8 V
FB2
VDDSSCG
C5
C13
C6 C14
VDDPLL
C17
C7 C15
VDDCML
C19
Serial
FPD-Link II
Interface
1.8 V
RTERM
RTERM
10 kQ
RMODE
I2C
Bus
Interface
FB3
FB4
Optional
C1
C2
C22
C23
VDDIO
RIN1+
RIN1-
RIN0+
RIN0-
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
MODE
PDB
SEL
OEN
OSS_SEL
BISTEN
RPU
C20
RPU
SCL
SDA
C21
Optional
RES_PIN43
DAP (GND)
VDDIO3
C10
ROUT0
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ROUT6
ROUT7
ROUT8
ROUT9
ROUT10
ROUT11
HS
VS
PCLK
LOCK
PASS
IDx[0]
LVCMOS
Parallel
Outputs
1.8 V
10 kQ
RID0
1.8 V
IDx[1]
10 kQ
RID1
NOTE:
C1, C22 = 0.1 µF (50 WV)
C2, C23 = 0.047 µF (50 WV)
C3 - C10 = 0.01 µF
C11 - C16 = 0.1 µF
C17 - C18 = 4.7 µF
C19 = 22 µF
C20 - C21 = >100 pF
RTERM = 50 Q
RPU = 1 kQ to 4.7 kQ
RID (see ID[x] Resistor Value Table)
FB1 - FB4: Impedance = 1 kQ (@ 100 MHz)
low DC resistance (<1 Q)
The "Optional" components shown are
provisions to provide higher system noise
immunity and will therefore result in higher
performance.
Copyright © 2016, Texas Instruments Incorporated
Figure 33. DS90UB914A-Q1 Typical Connection Diagram — Pin Control (Coax)
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Copyright © 2016, Texas Instruments Incorporated