DS90UB914A-Q1 Datasheet, PDF (20/61 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Deserializer

DS90UB914A-Q1
SNLS499A – APRIL 2016 – REVISED JUNE 2016
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Feature Description (continued)
8.3.4 Error Detection
The chipset provides error detection operations for validating data integrity in long distance transmission and
reception. The data error detection function offers users flexibility and usability of performing bit-by-bit data
transmission error checking. The error detection operating modes support data validation of the following signals:
• Bidirectional control channel data across the serial link
• Parallel video/sync data across the serial link
The chipset provides 1 parity bit on the forward channel and 4 cyclic redundancy check (CRC) bits on the back
channel for error detection purposes. The DS90UB913A/914A chipset checks the forward and back channel
serial links for errors and stores the number of detected errors in two 8-bit registers in the Serializer and the
Deserializer respectively.
To check parity errors on the forward channel, monitor registers 0x1A and 0x1B on the Deserializer. If there is a
loss of LOCK, then the counters on registers 0x1A and 0x1B are reset. Whenever there is a parity error on the
forward channel, the PASS pin will go low.
To check CRC errors on the back-channel, monitor registers 0x0A and 0x0B on the Serializer.
8.3.5 Synchronizing Multiple Cameras
For applications requiring multiple cameras for frame-synchronization, it is recommended to utilize the General
Purpose Input/Output (GPIO) pins to transmit control signals to synchronize multiple cameras together. To
synchronize the cameras properly, the system controller needs to provide a field sync output (such as a vertical
or frame sync signal) and the cameras must be set to accept an auxiliary sync input. The vertical synchronize
signal corresponds to the start and end of a frame and the start and end of a field. Note this form of
synchronization timing relationship has a non-deterministic latency. After the control data is reconstructed from
the bidirectional control channel, there will be a time variation of the GPIO signals arriving at the different target
devices (between the parallel links). The maximum latency delta (t1) of the GPIO data transmitted across
multiple links is 25 µs.
NOTE
The user must verify that the timing variations between the different links are within their
system and timing specifications.
See Figure 13 for an example of this function.
The maximum time (t1) between the rising edge of GPIO (that is, sync signal) to the time the signal arrives at
Camera A and Camera B is 25 µs.
20
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