DS90UB914A-Q1 Datasheet, PDF (24/61 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Deserializer

DS90UB914A-Q1
SNLS499A – APRIL 2016 – REVISED JUNE 2016
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Device Functional Modes (continued)
When the DS90UB913A-Q1 device is operated using an external oscillator, the GPO3 pin on the DS90UB913A-
Q1 is the input pin for the external oscillator. In applications where the DS90UB913A-Q1 device is operated from
an external oscillator, the divide-by-2 circuit in the DS90UB913A-Q1 device feeds back the divided clock output
to the imager device through GPO2 pin. The pixel clock to external oscillator ratios needs to be fixed for the
12–bit high frequency mode and the 10–bit mode. In the 10-bit mode, the pixel clock frequency divided by
the external oscillator frequency must be 2. In the 12-bit high frequency mode, the pixel clock frequency
divided by the external oscillator frequency must be 1.5. For example, if the external oscillator frequency is
48 MHz in the 10–bit mode, the pixel clock frequency of the imager needs to be twice of the external oscillator
frequency, that is, 96 MHz. If the external oscillator frequency is 48MHz in the 12-bit high frequency mode, the
pixel clock frequency of the imager needs to be 1.5 times of the external oscillator frequency, that is, 72 MHz. In
external oscillator mode, GPO2 and GPO3 on the Serializer cannot act as the output of the input signal coming
from GPIO2 or GPIO3 on the Deserializer.
8.4.2 DS90UB913A/914A Operation with Pixel Clock from Imager as Reference Clock
The DS90UB913A/914A chipsets can be operated by using the pixel clock from the imager as the reference
clock. Figure 17 shows the operation of the DS90UB913A/914A chipsets using the pixel clock from the imager. If
the DS90UB913A-Q1 device is operated using the pixel clock from the imager as the reference clock, then the
imager uses an external oscillator as its reference clock. There are 4 GPIOs available in this mode (PCLK from
imager mode).
Image
Sensor
Camera Unit
Serializer
Camera Data
10 or 12
YUV
HSYNC
VSYNC
SDA
SCL
DIN[11:0] or
DIN[9:0]
FV,LV
SDA
SCL
4
GPO
GPO[3:0]
PLL
Pixel Clock _PCLK
Deserializer
FPD-Link III
DOUT+
RIN0+
DOUT-
RIN0-
Bi-Directional
Back Channel
RIN1+
ROUT[11:0]
or
ROUT[9:0]
FV, LV
PCLK
Camera Data
10 or 12
YUV
HSYNC
VSYNC
Pixel Clock
RIN1-
GPIO[3:0]
SDA
SCL
4
GPIO
SDA
SCL
ECU Module
Microcontroller
Ext.
Oscillator
Copyright © 2016, Texas Instruments Incorporated
Figure 17. DS90UB913A-Q1/914A-Q1 Operation in PCLK mode
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Copyright © 2016, Texas Instruments Incorporated