DS90UB914A-Q1 Datasheet, PDF (35/61 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Deserializer

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DS90UB914A-Q1
SNLS499A – APRIL 2016 – REVISED JUNE 2016
Register Maps (continued)
Table 6. DS90UB914A-Q1 Control Registers⁽¹⁾ (continued)
ADDR
(HEX)
NAME
BITS FIELD
R/W
7
RX Parity Checker
Enable
RW
6
TX CRC Checker
Enable
RW
5 V_DDIO Control
RW
4 V_DDIO Mode
RW
DEFAULT
1
1
1
0
3 I2C Pass-Through
RW
1
0x03
General
Configuration 1
2 AUTO ACK
RW
0
1 Parity Error Reset
RW
0
0 RRFB
RW
1
0x04
0x05
EQ Feature
Control
EQ level - when
AEQ bypass is
7:4 enabled EQ setting RW
is provided by this
register
0000
3:0 RSVD
Reserved.
RW
0x00'h
0x06
SER ID
7:1 Remote ID
0 Freeze Device ID
RW
0
DESCRIPTION
Forward Channel Parity Checker Enable.
1: Enable.
0: Disable.
Back Channel CRC Generator Enable.
1: Enable.
0: Disable.
Auto voltage control.
1: Enable (auto detect mode).
0: Disable.
V_DDIO voltage set.
1: 3.3 V
0: 1.8 V
I2C Pass-Through Mode.
1: Pass-Through Enabled. SER Alias 0x07 and
Slave Alias 0x09- 0x17.
0: Pass-Through Disabled.
Automatically Acknowledge I2C Remote Write
When enabled, I2C writes to the Deserializer
(or any remote I2C Slave, if I2C PASS ALL is
enabled) are immediately acknowledged
without waiting for the Deserializer to
acknowledge the write. The accesses are then
remapped to address specified in 0x06. This
allows I2C bus without LOCK.
1: Enable.
0: Disable.
Parity Error Reset, This bit is NOT self-clearing.
1: Parity Error Reset.
0: No effect.
Pixel Clock Edge Select.
1: Parallel Interface Data is strobed on the
Rising Clock Edge.
0: Parallel Interface Data is strobed on the
Falling Clock Edge.
Equalization gain values listed below are @
maximum line rate (1.4 Gbps).
0000 = ~16.5 dB (minimum)
0001 = ~19.0 dB
0011 = ~20.5 dB
0111 = ~22.0 dB
1111 = ~23.0 dB (maximum)
Reserved.
7-bit Serializer Device ID Configures the I2C
Slave ID of the remote Serializer. A value of 0
in this field disables I2C access to the remote
Serializer. This field is automatically configured
by the Bidirectional Control Channel once RX
Lock has been detected. Software may
overwrite this value, but should also assert the
FREEZE DEVICE ID bit to prevent overwriting
by the Bidirectional Control Channel.
1: Freeze Serializer Device ID Prevent auto-
loading of the Serializer Device ID from the
Forward Channel. The ID will be frozen at the
value written.
0: Update.
Copyright © 2016, Texas Instruments Incorporated
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