DS90UB914A-Q1 Datasheet, PDF (40/61 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Deserializer

DS90UB914A-Q1
SNLS499A – APRIL 2016 – REVISED JUNE 2016
www.ti.com
Register Maps (continued)
Table 6. DS90UB914A-Q1 Control Registers⁽¹⁾ (continued)
ADDR
(HEX)
NAME
BITS FIELD
R/W
7
OEN_OSS
Override
RW
0x1F
Mode and OSS
Select
6 OEN Select
RW
5 OSS Select
RW
4
MODE_OVERRID
E
RW
3
PIN_MODE_12–bit
HF mode
R
2
PIN_MODE_10-bit
mode
R
1
MODE_12–bit High
Frequency
RW
0
MODE_10–bit
mode
RW
7:1
BCC Watchdog
timer
RW
0x20
BCC Watchdog
Control
0
BCC Watchdog
Timer Disable
RW
7
I2C Pass-Through
All
RW
0x21
I2C Control 1
6:4
I2C SDA Hold
Time
RW
3:0 I2C Filter Depth
RW
DEFAULT
0
0
0
0
0
0
0
0
0x7F'h
(111_1111'b)
0
0
0x1'h
0x7'h
DESCRIPTION
Allows overriding OEN and OSS select coming
from Pins.
1: Overrides OEN/OSS_SEL selected by pins.
0: Does NOT override OEN/OSS_SEL select
by pins.
OEN configuration from register.
OSS_SEL configuration from register.
Allows overriding mode select bits coming from
forward-channel.
1: Overrides MODE select bits.
0: Does not override MODE select bits.
Status of mode select pin.
Status of mode select pin.
Selects 12-bit high frequency mode. This bit is
automatically updated by the mode settings
from MODE pin unless MODE_OVERRIDE is
SET.
1: 12-bit high frequency mode is selected.
0: 12-bit high frequency mode is not selected.
To select 12-bit low frequency mode by register
override, set 0x1F[1] = 0x1F[0] = 0
Selects 10-bit mode. This bit is automatically
updated by the mode settings from MODE pin
unless MODE_OVERRIDE is SET.
1: Enables 10-bit mode.
0: Disables 10-bit mode.
The watchdog timer allows termination of a
control channel transaction if it fails to complete
within a programmed amount of time. This field
sets the Bidirectional Control Channel
Watchdog Timeout value in units of 2ms. This
field should not be set to 0.
Disable Bidirectional Control Channel
Watchdog Timer.
1: Disables BCC Watchdog Timer operation.
0: Enables BCC Watchdog Timer operation.
1: Enable Forward Control Channel pass-
through of all I2C accesses to I2C IDs that do
not match the Deserializer I2C ID. The I2C
accesses are then remapped to address
specified in register 0x06 (SER ID).
0: Enable Forward Control Channel pass-
through only of I2C accesses to I2C IDs
matching either the remote Serializer ID or the
remote I2C IDs.
Internal SDA Hold Time This field configures
the amount of internal hold time provided for
the SDA input relative to the SCL input. Units
are 50ns.
I2C Glitch Filter Depth This field configures the
maximum width of glitch pulses on the SCL and
SDA inputs that will be rejected. Units are 10ns.
40
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