DS90UB914A-Q1 Datasheet, PDF (45/61 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Deserializer

www.ti.com
DS90UB914A-Q1
SNLS499A – APRIL 2016 – REVISED JUNE 2016
Application Information (continued)
Table 7. Power-Up Sequencing Constraints for DS90UB914A-Q1
Symbol
t₀
t₁
t₂
Description
V_DDIO Rise Time
V_DDIO to V_{DD_n} Delay
V_{DD_n} Rise Time
Test Conditions
Min
Typ
V_IL to V_IH on rising edge; Monotonic
signal ramp is required
0.05
V_IL of rising edge (V_DDIO) to V_IL of rising
edge (V_{DD_n})
V_PDB < V_{IL_VDDIO}; V_IL to V_IH on rising
edge; Monotonic signal ramp is required
0
0.05
Max
Units
1.5
ms
ms
1.5
ms
Once the link is established, the 914 must be reset to optimize the link performance using either of the following
methods:
1. Toggle the PDB power down reset pin, or:
2. Write the reset register 0x01[1] = 1 over I2C. This is a self-clearing register bit. It does not erase or reset
other registers in the 914A.
If the MODE on the 914A device is being set through register override (0x1F) instead of strap resistor on the
MODE pin, a register reset (0x[1]1 = 1) is required. Manually toggling the PDB pin will not perform the required
optimization.
ROUT[11:0]
RIN0
or
RIN1
PDB
(914A)
t₁
t₀
Figure 29. Suggested Timing of PDB RESET for DS90UB914A-Q1 Deserializer
Symbol
t₀
t₁
Table 8. PDB RESET Timing Constraints for DS90UB914A-Q1
Description
PDB minimum LOW pulse
width
Data Lock Time
Test Conditions
V_IL of falling edge to V_IL of rising edge
V_IH of rising edge
Min
Typ
2
5
15
Max
Units
ms
22
ms
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB914A-Q1
Submit Documentation Feedback
45