DS90UB914A-Q1 Datasheet, PDF (4/61 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Deserializer

DS90UB914A-Q1
SNLS499A – APRIL 2016 – REVISED JUNE 2016
5 Device Comparison Table
PART NUMBER
DS90UB914Q-Q1
DS90UB914A-Q1
FPD-III FUNCTION
Deserializer
Deserializer
PACKAGE
WQFN RHS (48)
WQFN RHS (48)
6 Pin Configuration and Functions
48-Pin WQFN
Package RHS
Top View
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TRANSMISSION MEDIA
STP
Coax or STP
PCLK FREQUENCY
10 to 100 MHz
25 to 100 MHz
MODE 37
CMLOUTP 38
CMLOUTN 39
VDDCML0 40
RIN0+ 41
RIN0- 42
RES 43
RES 44
VDDPLL 45
SEL 46
PASS 47
LOCK 48
DAP = GND
DS90UB914A-Q1
Deserializer
24 ROUT[0]
23 ROUT[1]
22 ROUT[2]
21 ROUT[3]
20 VDDIO2
19 ROUT[4]
18 ROUT[5]
17 VDDD
16 ROUT[6]
15 ROUT[7]
14 ROUT[8]
13 ROUT[9]
Pin Functions: DS90UB914A-Q1 Deserializer
PIN
I/O
NAME
NO.
DESCRIPTION
LVCMOS PARALLEL INTERFACE
ROUT[11:0]
11,12,13,14,
15,16,18,19,
21,22,23,24
Outputs,
LVCMOS
Parallel Data Outputs.
For 10-bit MODE, parallel outputs ROUT[9:0] are active. ROUT[11:10] are inactive and
should not be used. Any unused outputs (including ROUT[11:10]) should be No Connect.
For 12-bit MODE (HF or LF), parallel outputs ROUT[11:0] are active. Any unused outputs
should be No Connect.
HSYNC
Horizontal SYNC Output. Note: HS transition restrictions: 1. 12-bit Low-Frequency mode: No
10
Output, HS restrictions (raw) 2. 12-bit High-Frequency mode: No HS restrictions (raw) 3. 10-bit
LVCMOS mode: HS restricted to no more than one transition per 10 PCLK cycles. Leave open if
unused.
VSYNC
9
Output,
LVCMOS
Vertical SYNC Output. Note: VS transition restrictions: 1. 12-bit Low-Frequency mode: No
VS restrictions (raw) 2. 12-bit High-Frequency mode: No VS restrictions (raw) 3. 10-bit mode:
VS restricted to no more than one transition per 10 PCLK cycles. Leave open if unused.
PCLK
8
Output, Pixel Clock Output Pin.
LVCMOS Strobe edge set by RRFB control register.
4
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