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| DS90UB914A-Q1 Datasheet, PDF (12/61 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Deserializer | |||
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DS90UB914A-Q1
SNLS499A â APRIL 2016 â REVISED JUNE 2016
7.6 AC Timing Specifications (SCL, SDA) - I2C-Compatible
Over recommended supply and temperature ranges unless otherwise specified. (Figure 1)
PARAMETER
TEST CONDITIONS
MIN
RECOMMENDED INPUT TIMING REQUIREMENTS
fSCL
SCL Clock Frequency
Standard Mode
Fast Mode
Standard Mode
4.7
tLOW
SCL Low Period
Fast Mode
1.3
Standard Mode
4.0
tHIGH
SCL High Period
Fast Mode
0.6
tHD:STA
Hold time for a start or a repeated start Standard Mode
condition
Fast Mode
4.0
0.6
tSU:STA
Set Up time for a start or a repeated
start condition
Standard Mode
Fast Mode
4.7
0.6
Standard Mode
0
tHD:DAT Data Hold Time
Fast Mode
0
Standard Mode
250
tSU:DAT Data Set Up Time
Fast Mode
100
Standard Mode
4.0
tSU:STO Set Up Time for STOP Condition
Fast Mode
0.6
Standard Mode
4.7
tBUF
Bus Free time between Stop and Start
Fast Mode
1.3
tr
SCL & SDA Rise Time
Standard Mode
Fast Mode
tf
SCL & SDA Fall Time
Standard Mode
Fast Mode
www.ti.com
NOM
MAX UNIT
100 kHz
400 kHz
µs
µs
µs
µs
µs
µs
µs
µs
3.45 µs
900 ns
ns
ns
µs
µs
µs
µs
1000 ns
300 ns
300 ns
300 ns
12
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