DS90UB914A-Q1 Datasheet, PDF (44/61 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Deserializer

DS90UB914A-Q1
SNLS499A – APRIL 2016 – REVISED JUNE 2016
9 Application and Implementation
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NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DS90UB914A was designed as a deserializer to support automotive camera designs. Automotive cameras
are often located in remote positions such as bumpers or trunk lids, and a major component of the system cost is
the wiring. For this reason it is desirable to minimize the wiring to the camera. This chipset allows the video data,
along with a bidirectional control channel, and power to all be sent over a single coaxial cable. The chipset is
also able to transmit over STP and is pin-to-pin/backwards compatible with the DS90UB914Q.
9.1.1 Power Over Coax
See application report Sending Power over Coax in DS90UB913A Designs for more details.
9.1.2 Power-Up Requirements and PDB Pin
The PDB pin on the device must be ramped after the V_DDIO and V_{DD_n} supplies have reached their required
operating voltage levels. It is recommended to assert PDB = HIGH with a control signal from a microcontroller to
help ensure proper sequencing of the PDB pin after settling of the power supplies. If a microcontroller is not
available, an RC filter network can be used on the PDB pin as an alternative method for asserting the PDB
signal. Please refer to Power Down for device operation when powered down.
Common applications will tie the V_DDIO and V_{DD_n} supplies to the same power source of 1.8V typically. This is an
acceptable method for ramping the V_DDIO and V_{DD_n} supplies. The main constraint here is that the V_{DD_n} supply
does not lead in ramping before the V_DDIO system supply. This is noted in Figure 28 with the requirement of t₁≥ 0.
t₀
1.8 V or 3.3 V
VDDIO
GND
t₂
1.8V
VDD_n
GND
t₁
VDDIO
PDB⁽¹⁾
GND
(1) _{It is recommended to assert PDB = HIGH with a microcontroller rather than an RC filter}
network to help ensure proper sequencing of PDB pin after settling of power supplies.
Figure 28. Suggested Power-Up Sequencing
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