DS90UB914A-Q1 Datasheet, PDF (2/61 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Deserializer

DS90UB914A-Q1
SNLS499A – APRIL 2016 – REVISED JUNE 2016
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Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Device Comparison Table..................................... 4
6 Pin Configuration and Functions ......................... 4
7 Specifications......................................................... 7
7.1 Absolute Maximum Ratings ...................................... 7
7.2 ESD Ratings.............................................................. 7
7.3 Recommended Operating Conditions....................... 7
7.4 Thermal Information .................................................. 8
7.5 Electrical Characteristics .......................................... 8
7.6 AC Timing Specifications (SCL, SDA) - I2C-
Compatible ............................................................... 12
7.7 Bidirectional Control Bus DC Timing Specifications
(SCL, SDA) - I2C-Compatible ................................. 13
7.8 Deserializer Switching Characteristics.................... 15
7.9 Typical Characteristics ............................................ 17
8 Detailed Description ............................................ 18
8.1 Overview ................................................................. 18
8.2 Functional Block Diagram ....................................... 18
8.3 Feature Description................................................. 19
8.4 Device Functional Modes........................................ 22
8.5 Programming .......................................................... 29
8.6 Register Maps ......................................................... 34
9 Application and Implementation ........................ 44
9.1 Application Information............................................ 44
9.2 Typical Applications ................................................ 47
10 Power Supply Recommendations ..................... 51
11 Layout................................................................... 52
11.1 Layout Guidelines ................................................. 52
11.2 Layout Example .................................................... 53
12 Device and Documentation Support ................. 55
12.1 Documentation Support ....................................... 55
12.2 Community Resources.......................................... 55
12.3 Trademarks ........................................................... 55
12.4 Electrostatic Discharge Caution ............................ 55
12.5 Glossary ................................................................ 55
13 Mechanical, Packaging, and Orderable
Information ........................................................... 55
4 Revision History
Changes from Original (April 2016) to Revision A
Page
• Split document into two separate documents for parts DS90UB913A-Q1 SNLS443 and DS90UB914A-Q1 SNLS499. ..... 1
• Combined revision history showing changes when this document was part of the DS90UB913A-Q1 SNLS443 datasheet 1
• Added Automotive Features ................................................................................................................................................... 1
• Updated pin description for ROUT to include active/inactive outputs corresponding to MODE setting................................. 4
• Added pin description to GPIO pins to leave open if unused. ............................................................................................... 5
• Updated frequency requirements for 10-bit and 12-bit HF modes. 10-bit mode – 50 MHz to 100 MHz; 12-bit HF
mode – 37.5 MHz to 75 MHz; 12-bit LF mode (no change) – 25 MHz to 50 MHz. .............................................................. 5
• Added pin description to RIN pins to leave open if unused. ................................................................................................. 6
• Changed Air Discharge ESD Rating (IEC61000-4-2: RD = 330 Ω, CS = 150 pF) to minimum ±25000 V. .......................... 7
• Added additional thermal characteristics................................................................................................................................ 8
• Added GPIO[3:0] typical pin capacitances. ........................................................................................................................... 8
• Changed Differential Input Voltage minimum specification. ................................................................................................... 9
• Changed Single-Ended Input Voltage minimum specification................................................................................................ 9
• Added Back Channel Differential Output Voltage minimum specification. ............................................................................. 9
• Added Back Channel Single-Ended Output Voltage minimum specification.......................................................................... 9
• Added footnote that states the following: “UI – Unit Interval is equivalent to one serialized data bit width. The UI
scales with PCLK frequency.” Also added below calculations to footnote. 12-bit LF mode 1 UI = 1 / ( PCLK_Freq. x
28 ) 12-bit HF mode 1 UI = 1 / ( PCLK_Freq. x 2/3 x 28 ) 10-bit mode 1 UI = 1 / ( PCLK_Freq. /2 x 28 ) .......................... 9
• Updated I_DDIOR for V_DDIO=1.89V, C_L=8pF, Worst-Case Pattern with f=50 MHz, 12-bit low freq mode to typical value of
16 mA; value is currently 21 mA. ........................................................................................................................................ 10
• Updated I_DDIOR for V_DDIO=1.89V, C_L=8pF, Random Pattern with f=50 MHz, 12-bit low freq mode to typical value of 10
mA; value is currently 14 mA................................................................................................................................................ 10
• Updated I_DDR for V_{DD_n}=1.89V, C_L=4pF, Random Pattern with f=100 MHz, 10-bit mode to typical value of 69 mA;
value is currently 57 mA. ..................................................................................................................................................... 10
• Updated I_DDR for V_{DD_n}=1.89V, C_L=4pF, Random Pattern with f=75 MHz, 12-bit high freq mode to typical value of 71
mA; value is currently 60 mA................................................................................................................................................ 10
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