DS90UB914A-Q1 Datasheet, PDF (28/61 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Deserializer

DS90UB914A-Q1
SNLS499A – APRIL 2016 – REVISED JUNE 2016
www.ti.com
Step 4. The link returns to normal operation after the deserializer BISTEN pin is low. Figure 20 shows the
waveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple
errors. In most cases, it is difficult to generate errors due to the robustness of the link (differential data
transmission etc.), thus they may be introduced by greatly extending the cable length, faulting the interconnect,
or by reducing signal condition enhancements (Rx equalization).
Normal
Step 1: DES in BIST
BIST
Wait
Step 2: Wait, SER in BIST
BIST
start
Step 3: DES in Normal
Mode - check PASS
BIST
stop
Step 4: DES/SER in Normal
Figure 19. AT-Speed BIST System Flow Diagram
BISTEN
(DES)
LOCK
PCLK
(RFB = L)
ROUT[0:11],
HS, VS
DATA
(internal)
PASS
Prior Result
DATA
(internal)
PASS
Prior Result
Normal
X = bit error(s)
X
X
X
BIST Test
BIST Duration
Figure 20. BIST Timing Diagram
PASS
FAIL
BIST
Result
Held
Normal
28
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