DS90UB914A-Q1 Datasheet, PDF (31/61 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Deserializer

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DS90UB914A-Q1
SNLS499A – APRIL 2016 – REVISED JUNE 2016
Programming (continued)
8.5.4 Slave Clock Stretching
The I2C-compatible interface allows programming of the DS90UB913A-Q1, DS90UB914A-Q1, or an external
remote device (such as image sensor) through the bidirectional control. To communicate and synchronize with
remote devices on the I2C bus through the bidirectional control channel/MCU, the chipset utilizes bus clock
stretching (holding the SCL line low) during data transmission; where the I2C slave pulls the SCL line low
on the 9th clock of every I2C transfer (before the ACK signal). The slave device will not control the clock and
only stretches it until the remote peripheral has responded. The I2C master must support clock stretching to
operate with the DS90UB913A/914A chipset.
8.5.5 ID[x] Address Decoder on the Deserializer
The IDx[0] and IDx[1] pins on the Deserializer are used to decode and set the physical slave address of the
Deserializer (I2C only) to allow up to 16 devices on the bus using only two pins. The pins set one of 16 possible
addresses for each Deserializer device. As there will be more Deserializer devices connected on the same board
than Serializers, more I2C device addresses have been defined for the DS90UB914A-Q1 Deserializer than the
DSDS90UB913A-Q1 Serializer. The pins must be pulled to V_DD (1.8 V, not V_DDIO) with a 10-kΩ resistor and two
pulldown resistors (R_ID0 and R_ID1) of the recommended value to set the physical device address. The
recommended maximum resistor tolerance is 1%.
1.8 V
1.8 V
10 k
10 k
VDDIO
RID1
RPU
RPU
HOST
SCL
SDA
RID0
IDx[0]
IDx[1]
Deserializer
SCL
SDA
To other
Devices
Copyright © 2016, Texas Instruments Incorporated
Figure 26. ID[x[ Address Decoder on the Deserializer
Copyright © 2016, Texas Instruments Incorporated
Product Folder Links: DS90UB914A-Q1
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