DS90UB914A-Q1 Datasheet, PDF (3/61 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Deserializer

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DS90UB914A-Q1
SNLS499A – APRIL 2016 – REVISED JUNE 2016
Revision History (continued)
• Updated I_DDR for V_{DD_n}=1.89V, C_L=4pF, Random Pattern with f=50 MHz, 12-bit low freq mode to typical value of 67
mA; value is currently 56 mA................................................................................................................................................ 10
• Updated V_OL Output Low Level row with revised I_OL currents and max V_OL voltages, dependent upon V_DDIO voltage........ 13
• Updated Figure 2 title to state ‘“Worst-Case” Test Pattern for Power Consumption’ .......................................................... 13
• Updated Figure 3 “Deserializer Vswing Diagram” with correct notation. ............................................................................. 13
• Changed Figure 3 to clarify difference between STP and Coax .......................................................................................... 13
• Updated frequency ranges for MODE settings and also revised with correct maximum clock periods. Added footnote
and nominal clock period to be in terms of 'T'. ..................................................................................................................... 15
• Changed typo on footnote to reflect 't_DPJ'. ............................................................................................................................ 16
• Added footnote to Figure 11 "Jitter amplitude max (~ 0.61UI) is limited by instrumentation and actual jitter amplitude
max of in-band jitter at low frequency is greater than 1 UI." ................................................................................................ 17
• Table 2, row 5 with “static” input LOCK output status changed to “L”. ............................................................................... 26
• Table 5 heading updated to state “DS90UB914A-Q1 DESERIALIZER. ............................................................................. 32
• Changed description of deserializer reg 0x00 bit[0]=0 from "set using address coming from CAD" to "set from ID[x]" ..... 34
• Added row to register 0x01[2] for Back Channel Enable – 0: Disable 1: Enable................................................................. 34
• Changed SSCG Units for fmod (register 0x02[3:0]) to Reflect Hz instead of KHz............................................................... 34
• Changed parity error reset bit to be NOT self-clearing. ...................................................................................................... 35
• Changed EQ gain values (dB) @ maximum line rate (1.4Gbps). ........................................................................................ 35
• Changed description of deserializer reg 0x04 to have correct register setting for each equalization gain level. ................ 35
• Added registers 0x26, 0x46 for Bidirectional Control Channel (BCC)Tuning. ..................................................................... 42
• Added deserializer 0x4C SEL register.................................................................................................................................. 43
• Updated EQ Register Bits 0x4E[3:0] to be Reserved. Also changed EQ gain values (dB) @ maximum line rate
(1.4Gbps).............................................................................................................................................................................. 43
• Added reference to Power over Coax Application report ..................................................................................................... 44
• Updated power up sequencing information and timing diagram. ........................................................................................ 44
• Added power up sequencing information and timing diagram. ............................................................................................ 44
• Added 914A PDB Reset timing constraints and diagram. ................................................................................................... 45
• Removed Figure 21 and Figure 43 regarding adaptive equalizer graphs for loss compensation (Coax/STP). .................. 46
• Renamed C1 and C2 to C22 and C23 for RIN0+ and RIN0- respectively on Typical Application Diagrams (Coax &
STP). .................................................................................................................................................................................... 48
• Added description specifying that the voltage applied on V_DDIO (1.8V, 3.3V) or V_{DD_n} (1.8V) should be at the input
pin – any board level DC drop should be compensated. .................................................................................................... 51
• Added 914A EVM layout example image. ........................................................................................................................... 54
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