DS90UB914A-Q1 Datasheet, PDF (41/61 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Deserializer

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DS90UB914A-Q1
SNLS499A – APRIL 2016 – REVISED JUNE 2016
Register Maps (continued)
Table 6. DS90UB914A-Q1 Control Registers⁽¹⁾ (continued)
ADDR
(HEX)
NAME
BITS FIELD
R/W
7
Forward Channel
Sequence Error
R
6
Clear Sequence
Error
RW
5 RSVD
4:3 SDA Output Delay RW
0x22
I2C Control 2
2 Local Write Disable RW
1
I2C Bus Timer
Speedup
RW
0
I2C Bus Timer
Disable
RW
0x23
General Purpose
Control
7:0 GPCR
RW
7:4 RSVD
0x24
BIST Control
3
BIST Pin
Configuration
RW
2:1 BIST Clock Source RW
0 BIST Enable
RW
0x25 Parity Error Count 7:0 BIST Error Count
R
DEFAULT
0
0
00
0
0
0
0x00'h
1
00
0
0x00'h
DESCRIPTION
Control Channel Sequence Error Detected This
bit indicates a sequence error has been
detected in forward control channel.
1: If this bit is set, an error may have occurred
in the control channel operation.
0: No forward channel errors have been
detected on the control channel.
1: Clears the Sequence Error Detect bit.
0: No effect.
Reserved.
SDA Output Delay This field configures output
delay on the SDA output. Setting this value will
increase output delay in units of 50ns. Nominal
output delay values for SCL to SDA are:
00 : ~350 ns
01: ~400 ns
10: ~450 ns
11: ~500 ns
Disable Remote Writes to local registers
Setting this bit to a 1 will prevent remote writes
to local device registers from across the control
channel. This prevents writes to the
Deserializer registers from an I2C master
attached to the Serializer. Setting this bit does
not affect remote access to I2C slaves at the
Deserializer.
Speed up I2C Bus Watchdog Timer.
1: Watchdog Timer expires after approximately
50 µs.
0: Watchdog Timer expires after approximately
1 s.
Disable I2C Bus Watchdog Timer When the
I2C Watchdog Timer may be used to detect
when the I2C bus is free or hung up following
an invalid termination of a transaction. If SDA is
high and no signaling occurs for approximately
1 second, the I2C bus will assumed to be free.
If SDA is low and no signaling occurs, the
device will attempt to clear the bus by driving 9
clocks on SCL.
Scratch Register.
Reserved.
Bist Configured through Pin.
1: Bist configured through pin.
0: Bist configured through register bit
"reg_24[0]".
BIST Clock Source.
See Table 4
BIST Control.
1: Enabled.
0: Disabled.
Number of Forward Channel Parity errors in
BIST mode.
Copyright © 2016, Texas Instruments Incorporated
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