DS90UB914A-Q1 Datasheet, PDF (42/61 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Deserializer

DS90UB914A-Q1
SNLS499A – APRIL 2016 – REVISED JUNE 2016
www.ti.com
Register Maps (continued)
Table 6. DS90UB914A-Q1 Control Registers⁽¹⁾ (continued)
ADDR
(HEX)
0x26
NAME
Bidirectional
Control Channel
(BCC) Tuning for
Channel 0 (RIN0±)
BITS
7:6
5:4
3:2
FIELD
RSVD
RSVD
Termination
Resistance Control
0x27 -
0x3B
1:0 RSVD
7:2 RSVD
0x3C
Oscillator output
divider select
1:0
OSC OUT
DIVIDER SEL
0x3D -
0x3E
0x3F
CML Output
Enable
7:5 RSVD
4 CML OUT Enable
3:0 RSVD
0x40 SCL High Time 7:0 SCL High Time
0x41
SCL Low Time
7:0 SCL Low Time
0x42 CRC Force Error
0x43 -
0x45
7:2 RSVD
1
Force Back
Channel Error
0
Force One Back
Channel Error
R/W
DEFAULT DESCRIPTION
Reserved.
Reserved.
00: 50 Ω (default)
RW
00
01: 47.4 Ω
10: 45.3 Ω
11: 37.7 Ω
Reserved.
Reserved.
Reserved.
Selects the divider for the OSC clock out on
PCLK when system is not locked and selected
RW
00
by OEN/OSS_SEL 0x02[5]:
00: 50 M (±30%)
01: 25 M (±30%)
1X: 12.5 M (±30%)
Reserved.
Reserved.
CML Output Driver Enable is Active-Low.
RW
1
0: CML Loop-through Driver is powered up.
1: CML Loop-through Driver is powered down.
Reserved.
I2C Master SCL High Time This field configures
the high pulse width of the SCL output when
the De-Serializer is the Master on the local I2C
RW
0x82'h
(1000_0010'b)
bus. Units are 50 ns for the nominal oscillator
clock frequency. The default value is set to
provide a minimum (4 μs + 0.3 μs of rise time
for cases where rise time is very fast) SCL high
time with the internal oscillator clock running at
26 MHz rather than the nominal 20 MHz.
I2C SCL Low Time This field configures the low
pulse width of the SCL output when the De-
Serializer is the Master on the local I2C bus.
This value is also used as the SDA setup time
by the I2C Slave for providing data prior to
RW
0x82'h
(1000_0010'b)
releasing SCL during accesses over the
Bidirectional Control Channel. Units are 50 ns
for the nominal oscillator clock frequency. The
default value is set to provide a minimum (4.7
µs + 0.3 µs of fall time for cases where fall time
is very fast) SCL low time with the internal
oscillator clock running at 26 MHz rather than
the nominal 20 MHz.
Reserved.
1: This bit introduces multiple errors into Back
RW
0
channel frame.
0: No effect.
1: This bit introduces ONLY one error into Back
RW
0
channel frame. Self clearing bit.
0: No effect.
Reserved.
42
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