DS90UB914A-Q1 Datasheet, PDF (34/61 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Deserializer

DS90UB914A-Q1
SNLS499A – APRIL 2016 – REVISED JUNE 2016
www.ti.com
8.6 Register Maps
ADDR
(HEX)
0x00
0x01
0x02
NAME
I2C Device ID
Reset
General
Configuration 0
Table 6. DS90UB914A-Q1 Control Registers⁽¹⁾
BITS FIELD
7:1 DEVICE ID
0
Deserializer ID
Select
7:6 RSVD
5 ANAPWDN
4:3 RSVD
2 BC Enable
1 Digital Reset 1
0 Digital Reset 0
7 RSVD
6 RSVD
5 Auto-Clock
4 SSCG LFMODE
3:0 SSCG
R/W
DEFAULT DESCRIPTION
RW
0xC0'h
7-bit address of Deserializer; 0x60'h.
(110_0000'b) default
RW
(1100_0000'b) _{0: Deserializer Device ID is set from ID[x].}
1: Register I2C Device ID overrides ID[x].
Reserved.
This register can be set only through local I2C
access.
RW
0
1: Analog power down: Powers down the
analog block in the Serializer.
0: No effect.
Reserved.
Back Channel Enable
RW
1
0: Disable
1: Enable
Digital Reset Resets the entire digital block
RW
0
except registers. This bit is self-clearing.
1: Reset.
0: No effect.
Digital Reset Resets the entire digital block
RW
0
including registers. This bit is self-clearing.
1: Reset.
0: No effect.
Reserved.
Reserved.
1: Output PCLK or OSC clock when not
RW
0
LOCKED.
0: Only PCLK.
1: Selects 8x mode for 10-18 MHz frequency
RW
0
range in SSCG.
0: SSCG running at 4X mode.
SSCG Select.
0000: Normal Operation, SSCG OFF.
0001: fmod (Hz) PCLK/2168, fdev ±0.50%.
0010: fmod (Hz) PCLK/2168, fdev ±1.00%.
0011: fmod (Hz) PCLK/2168, fdev ±1.50%.
0100: fmod (Hz) PCLK/2168, fdev ±2.00%.
0101: fmod (Hz) PCLK/1300, fdev ±0.50%.
0110: fmod (Hz) PCLK/1300, fdev ±1.00%.
0111: fmod (Hz) PCLK/1300, fdev ±1.50%.
RW
0
1000: fmod (Hz) PCLK/1300, fdev ±2.00%.
1001: fmod (Hz) PCLK/868, fdev ±0.50%.
1010: fmod (Hz) PCLK/868, fdev ±1.00%.
1011: fmod (Hz) PCLK/868, fdev ±1.50%.
1100: fmod (Hz) PCLK/868, fdev ±2.00%.
1101: fmod (Hz) PCLK/650, fdev ±0.50%.
1110: fmod (Hz) PCLK/650, fdev ±1.00%.
1111: fmod (Hz) PCLK/650, fdev ±1.50%.
Note: This register should be changed only
after disabling SSCG.
(1) To ensure optimum device functionality, It is recommended to NOT write to any RESERVED registers.
34
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