DS90UB914A-Q1 Datasheet, PDF (46/61 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Deserializer

DS90UB914A-Q1
SNLS499A – APRIL 2016 – REVISED JUNE 2016
www.ti.com
9.1.3 AC Coupling
The SER/DES supports only AC-coupled interconnects through an integrated DC-balanced decoding scheme.
External AC-coupling capacitors must be placed in series in the FPD-Link III signal path as illustrated in
Figure 30. For applications utilizing single-ended 50-Ω coaxial cable, the unused data pin (DOUT–, RIN–) should
utilize a 0.047-µF capacitor and should be terminated with a 50-Ω resistor.
SER
D_OUT+
D_OUT-
R_IN+
R_IN-
DES
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Figure 30. AC-Coupled Connection (STP)
D_OUT+
SER
D_OUT-
50Q
R_IN+
DES
50Q
R_IN-
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Figure 31. AC-Coupled Connection (Coaxial)
For high-speed FPD–Link III transmissions, the smallest available package should be used for the AC coupling
capacitor. This will help minimize degradation of signal quality due to package parasitics. The I/O’s require a 0.1-
µF AC coupling capacitors to the line.
9.1.4 Transmission Media
The DS90UB913A/914A chipset is intended to be used in a point-to-point configuration through a shielded
coaxial cable. The Serializer and Deserializer provide internal termination to minimize impedance discontinuities.
The interconnect (cable and connectors) should have a differential impedance of 100 Ω, or a single-ended
impedance of 50 Ω. The maximum length of cable that can be used is dependent on the quality of the cable
(gauge, impedance), connector, board(discontinuities, power plane), the electrical environment (for example,
power stability, ground noise, input clock jitter, PCLK frequency, etc). The resulting signal quality at the receiving
end of the transmission media may be assessed by monitoring the differential eye opening of the serial data
stream. A differential probe should be used to measure across the termination resistor at the CMLOUTP/N pins.
Figure 8 illustrates the minimum eye width and eye height that is necessary for bit error free operation.
Please refer to Cable Requirements for the DS90UB913A & DS90UB914A or contact TI for a channel
specification regarding cable loss parameters and further details on adaptive equalizer loss compensation.
9.1.5 Adaptive Equalizer – Loss Compensation
The receiver inputs provide an adaptive equalization filter in order to compensate for signal degradation from the
interconnect components. In order to determine the maximum cable reach, factors that affect signal integrity such
as jitter, skew, ISI, crosstalk, etc. need to be taken into consideration. The level of equalization can also be
manually selected via register controls. The adaptive equalized output can be seen using the
CMLOUTP/CMLOUTN pins in the Deserializer.
If the deserializer loses LOCK, the adaptive equalizer will reset and perform the LOCK algorithm again to
reacquire the video data stream being sent by the serializer.
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