DS90UB914A-Q1 Datasheet, PDF (5/61 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Deserializer

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DS90UB914A-Q1
SNLS499A – APRIL 2016 – REVISED JUNE 2016
Pin Functions: DS90UB914A-Q1 Deserializer (continued)
PIN
I/O
NAME
NO.
DESCRIPTION
GENERAL PURPOSE INPUT/OUTPUT (GPIO)
GPI0[1:0]
27,28
Digital
Input/Output,
LVCMOS
General-purpose input/output pins can be used to control and respond to various commands.
They may be configured to be the input signals for the corresponding GPOs on the serializer
or they may be configured to be outputs to follow local register settings. Leave open if
unused.
GPIO[3:2]
25,26
Digital
Input/Output
LVCMOS
General purpose input/output pins GPO[3:2] can be configured to be input signals for GPOs
on the Serializer. In addition they can also be configured to be outputs to follow the local
register settings. When the SerDes chipsets are working with an external oscillator, these
pins can be configured only to be outputs to follow the local register settings. Leave open if
unused.
BIDIRECTIONAL CONTROL BUS - I2C COMPATIBLE
SCL
SDA
MODE
2
Input/Output, Clock line for the bidirectional control bus communication.
Open Drain SCL requires an external pullup resistor to V_DDIO.
1
Input/Output, Data line for bidirectional control bus communication
Open Drain SDA requires an external pullup resistor to V_DDIO.
Device mode select pin
Resistor to Ground and 10-kΩ pullup to 1.8-V rail. The MODE pin on the Deserializer can be
used to configure the Serializer and Deserializer to work in different input PCLK range. See
details in Table 1.
12– bit low frequency mode – (25 – 50 MHz operation):
In this mode, the Serializer and Deserializer can accept up to 12-bits DATA+2 SYNC. Input
Input,
PCLK range is from 25 MHz to 50 MHz. Note: No HS/VS restrictions.
37
LVCMOS 12– bit high frequency mode – (37.5 – 75 MHz operation): In this mode, the Serializer and
w/ pull up Deserializer can accept up to 12-bits DATA + 2 SYNC. Input PCLK range is from 37.5 MHz
to 75 MHz. Note: No HS/VS restrictions.
10–bit mode– (50 – 100 MHz operation):
In this mode, the Serializer and Deserializer can accept up to 10-bits DATA + 2 SYNC. Input
PCLK frequency can range from 50 MHz to 100 MHz. Note: HS/VS restricted to no more
than one transition per 10 PCLK cycles.
Please refer to Table 1 on how to configure the MODE pin on the Deserializer.
IDx[0:1]
35,34
Input, analog
The IDx[0] and IDx[1] pins on the Deserializer are used to assign the I2C slave device
address. Resistor to Ground and 10-kΩ pullup to 1.8-V rail. See Table 5
CONTROL AND CONFIGURATION
PDB
30
Input,
LVCMOS
w/ pulldown
Power down Mode Input Pin.
PDB = H, Deserializer is enabled and is ON.
PDB = L, Deserializer is in power down mode. When the Deserializer is in power down
mode, programmed control register data are NOT retained and reset to default values.
LOCK
LOCK Status Output Pin.
48
Output, LOCK = H, PLL is Locked, outputs are active.
LVCMOS LOCK = L, PLL is unlocked, ROUT and PCLK output states are controlled by OSS_SEL
control register. May be used as Link Status.
BISTEN
6
Input
LVCMOS w/
pulldown
BIST Enable pin
BISTEN=H, BIST Mode is enabled.
BISTEN=L, BIST Mode is disabled.
See Built In Self Test for more information.
PASS
PASS Output Pin for BIST mode.
47
Output,
LVCMOS
PASS = H, ERROR FREE Transmission.
PASS = L, one or more errors were detected in the received payload.
See Built In Self Test for more information. Leave Open if unused. Route to test point (pad)
recommended.
OEN
5
Input
LVCMOS w/
pulldown
Output Enable Input.
Refer to Table 2.
OSS_SEL
4
Input
LVCMOS w/
pulldown
Output Sleep State Select Pin
Refer to Table 2.
Input
MUX Select line.
SEL
46
LVCMOS w/ SEL = L, RIN0+/- input. This selects input A as the active channel on the Deserializer.
pulldown SEL = H, RIN1+/- input. This selects input B as the active channel on the Deserializer.
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