DS90UB914A-Q1 Datasheet, PDF (14/61 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Deserializer

DS90UB914A-Q1
SNLS499A – APRIL 2016 – REVISED JUNE 2016
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RIN± 0V
PCLK
ROUTn
PDB ^VDDIO/2
R_IN±
t_DDLT
LOCK TRI-STATE
VDDIO/2
Figure 4. Deserializer Data Lock Time
Deserializer
8 pF
lumped
80%
20%
t_CLH
80%
20%
t_CHL
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Figure 5. Deserializer LVCMOS Output Load and Transition Times
SYMBOL N
SYMBOL N + 1
SYMBOL N + 2
SYMBOL N + 3
SYMBOL N + 3
SYMBOL N - 3
t_DD
SYMBOL N - 2
VDDIO/2
SYMBOL N - 1
SYMBOL N
SYMBOL N+1
Figure 6. Deserializer Delay
PCLK
ROUT[n],
VS, HS
t_RCP
1/2 V_DDIO
1/2 V_DDIO
1/2 V_DDIO
t_ROS
t_ROH
1/2 V_DDIO
V_DDIO
0V
V_DDIO
0V
Figure 7. Deserializer Output Setup/Hold Times
14
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Ew
EH
EH
t_BIT (1 UI)
VOD (+)
0V
VOD (-)
Figure 8. CML Output Driver
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Copyright © 2016, Texas Instruments Incorporated